Nonvolatile memory device and method of forming the nonvolatile memory device including giving an upper portion of an insulating layer an etching selectivity with respect to a lower portion

A nonvolatile memory device comprising:

• an active region of a semiconductor substrate defined between opposing device isolation layer segments;
• a tunnel insulating structure disposed on an upper surface of the active region;
• a charge storage structure comprising a lower charge storage structure disposed on the tunneling insulating structure and an upper charge storage structure disposed on the upper charge storing structure, wherein a width of the charge storage structure is less than or equal to a width of an upper surface of the active region;
• wherein each one of the opposing device isolation layer segments comprises an insulating layer filling a trench separating the active region from an adjacent active region of the semiconductor substrate, wherein the insulating layer comprises:
• opposing upper edge portions respectively disposed on at least a portion of a sidewall of the lower charge storage structure of the active region and on at least a portion of a sidewall of a lower charge storage structure of the adjacent active region, wherein the opposing upper edge portions extend no higher than an upper surface of the lower charge storage structure;
• spacers respectively disposed on the opposing upper edge portions, such that each spacer is disposed on at least a portion of a sidewall portion of the upper charge storage structure of the active region and at least a portion of a sidewall portion of the upper charge storage structure of the adjacent active region;
• and
• a recessed upper surface descending between the opposing upper edge portions to a centrally disposed nadir disposed between the active region and the adjacent active region;
• a gate interlayer dielectric layer conformally disposed over an upper surface of the upper charge storage structure, the spacers, and the recessed upper surface;
• and
• a control gate electrode disposed on the gate interlayer dielectric layer.