Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHong Sik Yoon, Jinshi Zhao, Ingyu Baek, Hyun Jun Sim, Minyoung Park
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.
Claims18
A semiconductor memory device comprising:
- a gate of a first wordline transistor disposed in a first region of a semiconductor substrate;
- a gate of a bitline transistor disposed in a second region of the semiconductor substrate;
- at least one first wordline channel pillar penetrating the gate of the first wordline transistor and insulated from the gate of the first wordline transistor;
- at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor;
- a local bitline extending in a first direction substantially vertical to an upper surface of the semiconductor substrate and electrically connected to the bitline channel pillar;
- a first local wordline disposed at one side of the local bitline, extending in a second direction substantially perpendicular to the first direction so as to intersect the local bitline, and electrically connected to the first wordline channel pillar;
- and
- a first memory cell formed at an intersection between the local bitline and the first local wordline.
A semiconductor memory device comprising:
- a gate of a wordline transistor disposed on a semiconductor substrate;
- a gate of a bitline transistor disposed on the semiconductor substrate;
- at least one wordline channel pillar penetrating the gate of the wordline transistor and insulated from the gate of the wordline transistor;
- at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor;
- a local bitline extending in a first direction and electrically connected to the bitline channel pillar;
- and
- a local wordline disposed at one side of the local bitline, extending in a second direction different from the first direction so as to intersect the local bitline, and electrically connected to the wordline channel pillar.
A system comprising:
- a semiconductor device comprising:
- a gate of a wordline transistor disposed on a semiconductor substrate;
- a gate of a bitline transistor disposed on the semiconductor substrate;
- at least one wordline channel pillar penetrating the gate of the wordline transistor and insulated from the gate of the wordline transistor;
- at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor;
- a local bitline extending in a first direction and electrically connected to the bitline channel pillar;
- and
- a local wordline disposed at one side of the local bitline, extending in a second direction different from the first direction so as to intersect the local bitline, and electrically connected to the wordline channel pillar;
- and
- a CPU or a controller coupled to the semiconductor device.
Dependencies are inferred from the claim text.