Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length

A computer readable medium having program instructions stored thereon for a semiconductor device layout, comprising:

• a layout of a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively;
• a layout of at least six linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first direction, and
• wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including,
• (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor,
• (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that,
• (i) the first N-transistor and the first P-transistor aligned along the first direction and electrically connected to each other through their gate defining shapes,
• ii) the gate defining shapes of the second N-transistor and the second P-transistor not electrically connected to each other,
• (iii) the gate defining shapes of the third N-transistor and third P-transistor not electrically connected to each other, and
• (iv) the fourth N-transistor and fourth P-transistor aligned along the first direction and electrically connected to each other through their gate defining shapes,
• wherein at least two of the gate defining shapes of the second N-transistor, third N-transistor, second P-transistor, and third P-transistor have different lengths as measured in the first direction.

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively;
• operating a computer to define at least six linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first direction, and
• wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including,
• (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor,
• (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that,
• (i) the first N-transistor and the first P-transistor aligned along the first direction and electrically connected to each other through their gate defining shapes,
• (ii) the gate defining shapes of the second N-transistor and the second P-transistor not electrically connected to each other,
• (iii) the gate defining shapes of the third N-transistor and third P-transistor not electrically connected to each other, and
• (iv) the fourth N-transistor and fourth P-transistor aligned along the first direction and electrically connected to each other through their gate defining shapes,
• wherein at least two of the gate defining shapes of the second N-transistor, third N-transistor, second P-transistor, and third P-transistor have different lengths as measured in the first direction.