Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size

A computer readable medium having program instructions stored thereon for a semiconductor device layout, comprising:

• a layout of a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively;
• a layout of at least four linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least four linear shapes has its lengthwise centerline extending in the first direction, and
• wherein some of the at least four linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, the at least four linear shapes including—
• a first gate defining shape including a gate portion that forms a gate electrode of a first transistor and an extending portion that extends away from the gate electrode of the first transistor by a first extension length as measured in the first direction,
• a second gate defining shape including a gate portion that forms a gate electrode of a second transistor and an extending portion that extends away from the gate electrode of the second transistor by a second extension length as measured in the first direction,
• a third gate defining shape including a gate portion that forms a gate electrode of a third transistor and an extending portion that extends away from the gate electrode of the third transistor by a third extension length as measured in the first direction,
• a fourth gate defining shape including a gate portion that forms a gate electrode of a fourth transistor and an extending portion that extends away from the gate electrode of the fourth transistor by a fourth extension length as measured in the first direction, and
• wherein at least two of the first, second, third, and fourth extension lengths are different.

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively;
• operating a computer to define at least four linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least four linear shapes has its lengthwise centerline extending in the first direction, and
• wherein some of the at least four linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, the at least four linear shapes including—
• a first gate defining shape including a gate portion that forms a gate electrode of a first transistor and an extending portion that extends away from the gate electrode of the first transistor by a first extension length as measured in the first direction,
• a second gate defining shape including a gate portion that forms a gate electrode of a second transistor and an extending portion that extends away from the gate electrode of the second transistor by a second extension length as measured in the first direction,
• a third gate defining shape including a gate portion that forms a gate electrode of a third transistor and an extending portion that extends away from the gate electrode of the third transistor by a third extension length as measured in the first direction,
• a fourth gate defining shape including a gate portion that forms a gate electrode of a fourth transistor and an extending portion that extends away from the gate electrode of the fourth transistor by a fourth extension length as measured in the first direction, and
• wherein at least two of the first, second, third, and fourth extension lengths are different.