Merged cascode transistor

A merged cascode high electron mobility transistor circuit comprises:

• an input voltage signal source having an input voltage signal;
• a constant voltage source having a predetermined constant voltage;
• a merged cascode transistor comprising:
• a first epitaxial layer of III-Nitride material;
• a second epitaxial layer of a III-Nitride material in contact with the first epitaxial layer such that a 2-dimensional electron gas conducting layer is formed between the first and second epitaxial layers;
• a source electrode electrically connected to the first epitaxial layer;
• a drain electrode electrically connected to the first epitaxial layer and spaced laterally from the source electrode;
• a first gate positioned between the source electrode and the drain electrode and coupled to the first epitaxial layer to form a first portion of the transistor;
• and
• a second gate, including a field plate, positioned adjacent to the first gate, and between the drain electrode and source electrode and coupled to the first epitaxial layer to form a second portion of the transistor;
• wherein the first gate is connected to the input voltage signal source such that conduction of the first portion is based on a value of the input voltage signal and the second gate is connected to the constant voltage source such that the second portion of the transistor conducts until a voltage difference between the predetermined constant voltage and a voltage at a node in the semiconductor element between the first portion and the second portion of the transistor reaches a predetermined level, wherein the first portion of the transistor is an enhancement mode transistor and the second portion of the transistor is a depletion mode transistor, and wherein a drain region of the enhancement mode transistor is merged with a source region of the depletion mode transistor at the node in the semiconductor element.