Bi-layer pseudo-spin field-effect transistor

A bi-layer pseudo-spin field-effect transistor (BiSFET) NOR gate comprising:

• a first and second inputs;
• an output;
• a first inverter includes
• a first BiSFET having a first gate, a second gate, a first conduction layer and a second conduction layer;
• and
• a second BiSFET having a third gate, a fourth gate, a third conduction layer and a fourth conduction layer, wherein said first input is connected to said first and fourth gates, wherein said first conduction layer is connected to a clock, and said fourth conduction layer is connected to ground;
• and
• a second inverter includes
• a third BiSFET having a fifth gate, a sixth gate, a fifth conduction layer and a sixth conduction layer;
• and
• a fourth BiSFET having a seventh gate, an eighth gate, a seventh conduction layer and an eighth conduction layer, wherein said second input is connected to said fifth and eigthth gates, said output is connected to said sixth and seventh conduction layers, wherein said fifth conduction layer is connected to said second and third conduction layers, and said eighth conduction layer is connected to ground.