Inverted variable resistance memory cell and method of making the same

A variable resistance memory cell, comprising:

• a first insulating layer, the first insulating layer formed over a substrate;
• a first electrode, a first portion of the first electrode arranged within a first portion of a via through the first insulating layer and a second portion of the first electrode arranged on sidewalls of the via, the second portion of the via having a substantially hemispherical shape;
• a variable resistance layer formed over the first electrode and within the second portion of the via;
• a second insulating layer being formed over the first insulating layer, the first electrode, and the variable resistance layer;
• and
• a second electrode arranged within a via through the second insulating layer.

A phase change memory bit structure, comprising:

• an access device;
• a cell select line;
• a bit line;
• a word line;
• and
• a phase change memory cell, the phase change memory cell comprising:
• a first insulating layer having an opening, a top portion of the opening being generally hemispherical;
• a first conductive layer formed over the opening, the first conductive layer having substantially uniform thickness along sidewalls of the top portion and substantially filling a bottom portion of the opening;
• a phase change material layer formed over the first conductive layer and within the top portion of the opening;
• a second insulating layer having an opening, the second insulating layer being formed over the first insulating layer, the first conductive layer, and the phase change material layer;
• and
• a second conductive layer formed over the second insulating layer, the second conductive layer substantially filling the opening of the second insulating layer,
• wherein the phase change memory cell is connected to the cell select line and coupled to the bit line through the access device gated by the word line.

A memory device, comprising:

• a phase change memory array, the phase change memory array comprising:
• a plurality of word lines;
• a plurality of cell select lines;
• a plurality of bit lines, and
• a plurality of memory bit structures, each of the memory bit structures including an access device and a phase change memory cell, the phase change memory cell being connected with one of the plurality of cell select lines and coupled with one of the plurality of bit lines through the access device gated by one of the plurality of word lines, the phase change memory cell comprising:
• a first insulating layer having an opening;
• a first metal layer formed over the opening, the metal layer having substantially uniform thickness along sidewalls of a top portion of the opening and substantially filling a bottom portion of the opening, the top portion of the opening being substantially hemispherical;
• a phase change material layer formed over the first metal layer, wherein the phase change material layer is substantially hemispherical;
• a second insulating layer having an opening, the second insulating layer being formed over the first insulating layer, the first metal layer, and the phase change material layer;
• and
• a second metal layer formed over the second insulating layer;
• and
• peripheral circuitry formed on a substrate and electrically connected to the phase change memory array.