High-yield method of exposing and contacting through-silicon vias

A method comprising the steps of:

• obtaining an assembly comprising:
• a main wafer having a body with a front side and a back side, said main wafer in turn comprising a plurality of blind electrical vias terminating above said back side, said blind electrical vias having conductive cores with surrounding insulator adjacent side and end regions of said cores;
• and
• a handler wafer, said handler wafer being secured to said front side;
• exposing said blind electrical vias, on said back side, wherein exposed portions of said blind electrical vias are of various heights across said back side after exposure;
• wherein said step of exposing said blind electrical vias comprises:
• thinning said wafer by removing material from said back side until said blind vias are almost exposed;
• and
• dry etching said back side to expose said vias to said various heights;
• applying a chemical mechanical polish process to said back side after said exposing step, to open any of said surrounding insulator adjacent said end regions of said cores remaining after said exposing step, and to co-planarize said via conductive cores, said surrounding insulator adjacent said side regions of said cores, and said body of said main wafer;
• etching said back side to produce a uniform standoff height of each of said vias across said back side;
• after said application of chemical mechanical polishing process
• depositing a dielectric across said back side;
• and
• applying a second chemical mechanical polish process to said back side, to open said dielectric only adjacent said conductive cores of said vias.