Structure for use in fabrication of PiN heterojunction TFET

A method for fabricating a device comprising a PiN heterojunction tunnel field effect transistor (TFET), the method comprising:

• forming an alignment trench in a silicon wafer;
• forming a silicon germanium (SiGe) growth trench in the silicon wafer;
• growing a p-type SiGe region in the SiGe growth trench;
• forming a first oxide layer over the alignment trench and the p-type SiGe region, wherein the first oxide layer fills the alignment trench;
• forming a hydrogen implantation region in the silicon wafer underneath the p-type SiGe region and the alignment trench, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region, and wherein the upper silicon region comprises the alignment trench and the p-type SiGe region;
• bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer, wherein the bonded oxide layer fills the alignment trench;
• separating the lower silicon region from the upper silicon region at the hydrogen implantation region;
• and
• forming the PiN heterojunction TFET using the upper silicon region, wherein the p-type SiGe region comprises a p-type region of a PiN heterojunction that comprises a tunnel barrier of the PiN heterojunction TFET, and wherein the alignment trench is used to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region during formation of the device comprising the PiN heterojunction TFET.