Thin body semiconductor devices

A method for fabricating an FET device, said method comprising:

• providing a body over, and in direct contact with, an insulator, wherein said body and said insulator have a common interface, wherein said body has surfaces, including two opposing side surfaces essentially parallel with one another, and with each said side surface being substantially perpendicular to said common interface, wherein each said side surface is adapted to host a device channel;
• selecting said body of the group consisting of Si, Ge, and their alloy mixtures;
• wherein said body has a thickness, selecting said thickness to be below a critical thickness, wherein below said critical thickness said body is susceptible to agglomeration upon being heated above an agglomeration temperature, wherein said thickness separates said two side surfaces;
• forming a raised source/drain by a selective epitaxy, using said surfaces of said body for seeding said selective epitaxy;
• ahead of said selective epitaxy, clearing said surfaces of oxygen, wherein said clearing consists of heating said body layer under ultra high vacuum (UHV) conditions to a temperature not exceeding said agglomeration temperature;
• and
• wherein said FET device comprises said body, said device channel, and said raised source/drain, and wherein said FET device is characterized as being a non-planar semiconductor on insulator (SOI) device.