Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

A method, comprising:

• forming a first structure which defines a gate region of a field-effect transistor (FET), the first structure formed on a semiconductor region which will constitute a body region of the FET;
• sensitizing semiconductor material proximate to the first structure but not covered by the first structure to produce sensitized semiconductor material,
• covering the sensitized semiconductor material with an insulator
• removing a portion of the insulator, exposing a first portion of the sensitized semiconductor material and leaving a second portion of the sensitized semiconductor material covered with the insulator;
• selectively removing substantially all of the sensitized semiconductor material, creating a recess with an overhang of insulator;
• and
• depositing a metal in the recess to form a metal source/drain, said metal source/drain at least partly covered by said overhang of insulator.

A method of forming a transistor, comprising:

• forming a first material stack including a semiconductor, capped with a second material stack, the first and second material stacks each covering both an active region of the transistor and a region where a gate conductor of the transistor will extend over a field,
• forming a field insulator in a region not covered by the first and second material stacks,
• removing the second material stack from a first region of the gate conductor, which includes a channel region of the transistor, and a region where the gate conductor extends within a field region,
• forming a gate stack in the first region from which the second material stack was removed,
• removing remaining portions of the second material stack, forming a recess,
• depositing a metal source/drain in the recess.