Process margin engineering in charge trapping field effect transistors

A method comprising:

• forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount;
• oxidizing a portion of the substrate to form a blocking dielectric region;
• depositing a first set of one or more nitride layers on the blocking dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount;
• etching back a portion of the first set of one or more nitride layers to the tops of the trench isolation regions;
• depositing a second set of one or more nitride layers on the etched back first set of one or more nitride layers;
• oxidizing the second set of one or more nitride layers to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region;
• and
• depositing a gate region on the blocking dielectric region.

A method comprising:

• forming a plurality of shallow trench isolation regions on a substrate having a mesa height that extends above the substrate by a given amount;
• forming a tunneling dielectric region on a substrate;
• forming a first nitride layer on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first nitride layer is approximately half of given amount;
• etching back a portion of the first nitride layer to the tops of the mesas of the trench isolation regions to form a charge trapping region between the trenches;
• forming a second nitride layer on the charge trapping region and the tops of the mesas of the trench isolation regions;
• oxidizing the second nitride layer to form a blocking dielectric region on the charge trapping region;
• and
• forming a gate region on the blocking dielectric region.