Epitaxy profile engineering for FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
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Abstract
A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
Claims20
A method of forming an integrated circuit structure, the method comprising:
- providing a wafer comprising a substrate and a semiconductor fin at a major surface of the substrate;
- performing a first deposition step to epitaxially grow a first epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the first epitaxy layer comprises a semiconductor material;
- and
- after the step of performing the first deposition step, performing a first etch step to remove a portion of the first epitaxy layer, with a remaining portion of the first epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
A method of forming an integrated circuit structure, the method comprising:
- providing a wafer comprising a substrate and a semiconductor fin at a major surface of the substrate;
- forming a gate dielectric and a gate electrode covering a first portion of the semiconductor fin, with a second portion of the semiconductor fin uncovered by the gate dielectric and the gate electrode;
- and
- performing a first deposition-etch cycle comprising:
- performing a first deposition step to form a first epitaxy semiconductor layer on the second portion of the semiconductor fin;
- and
- performing a first etch step to reduce a thickness of the first epitaxy semiconductor layer, wherein the first deposition step and the first etch step are in-situ performed with no vacuum break therebetween.
A method of forming an integrated circuit structure, the method comprising:
- providing a wafer comprising:
- a semiconductor substrate;
- two shallow trench isolation (STI) regions in the semiconductor substrate;
- and
- a semiconductor fin over, and horizontally between, the two STI regions;
- forming a gate dielectric and a gate electrode covering a first portion of the semiconductor fin, with a second portion of the semiconductor fin uncovered by the gate dielectric and the gate electrode;
- and
- performing a plurality of deposition-etch cycles, each comprising:
- performing a deposition step to form an epitaxy layer over a top surface and sidewalls of the second portion of the semiconductor fin;
- and
- performing an etch step to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and sidewalls of the second portion of the semiconductor fin.
Dependencies are inferred from the claim text.