Asymmetric FinFET devices
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Bruce B. Doris, Ying Zhang
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Abstract
Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
Claims11
A method for fabricating FET devices, said method comprising:
- receiving a fin of a semiconductor material, wherein said fin has a first side surface opposite a second side surface;
- disposing over said fin a high-k dielectric layer followed by a threshold-modifying layer;
- performing an ion bombardment at a tilted angle, wherein said threshold-modifying layer over said first side surface is receiving said ion bombardment and over said second side surface is not receiving said ion bombardment due to being shadowed by said fin, wherein said ion bombardment removes said threshold-modifying layer over said first side surface;
- and
- following said ion bombardment, disposing a gate conductor layer over said fin, whereby said first side surface becomes adapted to host a first FET device and said second side surface becomes adapted to host a second FET device, wherein said first and said second FET device are asymmetric due to said threshold-modifying layer being present only in said second FET device.
A method for fabricating FET devices, said method comprising:
- receiving a fin of a semiconductor material, wherein said fin has a first side surface opposite a second side surface;
- disposing over said fin an ordered sequence of layers, said ordered sequence comprises a high-k dielectric layer, a first gate conductor layer, and a semiconductor front layer;
- performing an ion implantation at a tilted angle, wherein said semiconductor front layer over said first side surface is receiving said ion implantation and is not receiving said implantation over said second surface due to being shadowed by said fin, whereby said semiconductor front layer acquires a doped portion over said first side surface;
- selectively etching said doped portion, whereby leaving in place a remaining portion of said semiconductor front layer, therein exposing said first gate conductor layer over said first side surface;
- etching away said first gate conductor layer over said first side surface followed by etching away said remaining portion of said semiconductor front layer;
- and
- disposing a second gate conductor layer over said fin, whereby said first side surface becomes adapted to host a first FET device and said second side surface becomes adapted to host a second FET device, wherein said first and second FET device have an asymmetry due differing in said second and said first gate conductor layer.
Dependencies are inferred from the claim text.