Semiconductor device and method of manufacturing the same
AssigneeSeiko Instruments Inc.
InventorsHideo Yoshino, Hisashi Hasegawa
Life of this patent
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Abstract
Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.
Claims7
A method of manufacturing a semiconductor device comprising a first conductivity type MOS transistor formed on a silicon active layer of an SOI substrate, the method comprising:
- forming a LOCOS isolation region having a thickness sufficient to contact a buried insulating film and define a MOS transistor region in the silicon active layer;
- forming a gate insulating film having a thickness of about 5 to 30 nm in the MOS transistor region by thermal oxidation;
- forming a polysilicon layer having a thickness of 200 to 400 nm on the gate insulating film;
- a first impurity doping step comprising doping an impurity in a portion of the polysilicon layer above a channel region of the silicon active layer to form:
- a first conductivity-type polysilicon region above the channel region of the silicon active layer, where the silicon active layer has a constant thickness;
- and
- second conductivity-type polysilicon regions above edges of the LOCOS isolation region, where the second conductivity-type is opposite to the first conductivity-type, and where a thickness of the silicon active layer decreases compared to the constant thickness;
- etching the polysilicon layer to form a gate electrode;
- a second impurity doping step comprising partially and selectively doping a first conductivity-type impurity in the silicon active layer in the MOS transistor region to define a source region and a drain region;
- forming an intermediate insulating layer on the SOI substrate;
- forming a contact hole in the intermediate insulating layer;
- forming a metal wiring in the contact hole;
- and
- forming a protective film.
A method of manufacturing a semiconductor device comprising a first conductivity-type MOS transistor formed on a silicon active layer of an SOI substrate, the method comprising:
- forming a LOCOS isolation region having a thickness sufficient to contact a buried insulating film and define a MOS transistor region in the silicon active layer;
- forming a gate insulating film having a thickness of about 5 to 30 nm in the MOS transistor region by thermal oxidation;
- forming a polysilicon layer having a thickness of 200 to 400 nm on the gate insulating film;
- a first impurity doping step comprising doping an impurity in a portion of the polysilicon layer above a channel region of the silicon active layer to form:
- a first conductivity-type polysilicon region above the channel region of the silicon active layer, where the silicon active layer has a constant thickness;
- and second conductivity-type polysilicon regions above edges of the LOCOS isolation region, where the second conductivity-type is opposite to the first conductivity-type, and where a thickness of the silicon active layer decreases compared to the constant thickness;
- etching the polysilicon layer to form a gate electrode;
- a second impurity doping step comprising partially and selectively doping a first conductivity-type impurity in the silicon active layer in the MOS transistor region to define a source region and a drain region;
- forming an intermediate insulating layer on the SOI substrate;
- forming a contact hole in the intermediate insulating layer;
- partially and selectively doping a second conductivity-type impurity in the source region through patterning with a photoresist after the second impurity doping step of doping a first conductivity type impurity;
- forming a metal wiring in the contact hole;
- and
- forming a protective film.
A method of manufacturing a semiconductor device comprising a first conductivity-type MOS transistor formed on a silicon active layer of an SOI substrate, the method comprising:
- forming a LOCOS isolation region having a thickness sufficient to contact a buried insulating film by thermal oxidation to define a MOS transistor region in the silicon active layer;
- forming a gate insulating film having a thickness of about 5 to 30 nm in the MOS transistor region by thermal oxidation;
- forming a polysilicon layer having a thickness of 200 to 400 nm on the gate insulating film;
- a first impurity doping step comprising doping an impurity in a portion of the polysilicon layer above a channel region of the silicon active layer to form:
- a first conductivity-type polysilicon region above the channel region of the silicon active layer, where the silicon active layer has a constant thickness;
- and
- second conductivity-type polysilicon regions above edges of the LOCOS isolation region, where the second conductivity-type is opposite to the first conductivity-type, and where a thickness of the silicon active layer decreases compared to the constant thickness;
- forming a refractory metal silicide having a thickness of 500 Å to 2500 Å on the polysilicon layer;
- etching the polysilicon layer and the refractory silicide to form a gate electrode;
- a second impurity doping step comprising partially and selectively doping a first conductivity-type impurity in the silicon active layer in the MOS transistor region to form a source and a drain;
- forming an intermediate insulating layer on the SOI substrate;
- forming a contact hole in the intermediate insulating layer;
- forming a metal wiring in the contact hole;
- and
- forming a protective film.
Dependencies are inferred from the claim text.