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US 8,263,440 B2Granted
Method for fabricating etching barrier by using shadow effect and method for fabricating one side contact of vertical transistor using the same
AssigneeSK hynix Inc.
InventorJun Ki Kim
Life of this patent
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Abstract
A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies.
Claims15
A method for fabricating one side contact of a vertical transistor, comprising:
- forming wall bodies on a semiconductor substrate, wherein each wall body comprises an active region, with a first trench in between adjacent wall bodies;
- forming a first liner on wall surfaces of the wall bodies;
- filling the first trench with a sacrificial layer;
- forming a second trench by recessing the first liner and the sacrificial layer, so that an upper portion of the first liner is exposed to a bottom edge portion of the second trench;
- forming an etching barrier by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein a first of two bottom edge portions of the trench is selectively covered by the etching barrier, and wherein the deposition is performed such that a second of the two bottom edge portions is not covered by the etching barrier due to a shadow effect by upper portions of the wall bodies;
- removing the first liner positioned at the edge portion not covered by the etching barrier;
- partially exposing the active region by selectively etching lower sidewalls of the wall bodies to form a groove, which is formed between the sacrificial and the wall bodies by the removal of the first liner, as a passage;
- and
- forming a bit line contacting the exposed active region.
6 more elements
A method for fabricating one side contact of a vertical transistor, comprising:
- forming wall bodies on a semiconductor substrate with a first trench in between adjacent wall bodies;
- forming a mask comprising a first region covering a portion of a lower sidewall of the wall body, a second region covering a lower portion of the first region, and a third region covering an upper portion of the first region, the first, second and third regions being formed of different materials;
- forming a first liner covering the first region and the third region of the mask;
- forming a sacrificial layer filling the first trench;
- forming a second trench by recessing the first liner and the sacrificial layer, so that an upper portion of the first liner is exposed to a bottom edge portion of the second trench;
- forming an etching barrier by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein the deposition is performed such that one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by the upper portions of the wall bodies;
- forming a groove exposing the first region of the mask by removing the first liner positioned at the edge portion not covered by the etching barrier;
- exposing a portion of a lower sidewalls of the wall bodies by removing the first region of the mask not covered by the etching barrier;
- and
- forming a bit line contacting the exposed portion of the lower sidewalls of the wall bodies.
7 more elements
Dependencies are inferred from the claim text.