Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction

A computer readable medium having program instructions stored thereon for a semiconductor device layout, comprising:

• a layout of a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively;
• a layout of at least six linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first direction, the at least six linear shapes spaced apart from each other in accordance with an integer multiple of a first pitch as measured in a second direction perpendicular to the first direction between lengthwise centerlines of the at least six linear shapes, wherein each linear shape within the gate layer region is spaced apart from at least one other linear shape by a lengthwise centerline-to-lengthwise centerline spacing as measured in the second direction that is substantially equal to the first pitch, and wherein all linear shapes within the gate layer region are within 1930 nanometers of each other, and
• wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including,
• (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor,
• (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that,
• (i) the first N and P transistors aligned along the first direction and electrically connected to each other through their gate defining shapes,
• (ii) the second N and P transistors aligned along the first direction and their gate defining shapes having extensions not electrically connected to each other,
• (iii) the third N and P transistors aligned along the first direction and their gate defining shapes having extensions not electrically connected to each other, and
• (iv) the fourth N and P transistors aligned along the first direction and electrically connected to each other through their gate defining shapes
• wherein either a) the N transistors are transistors of a first transistor type and the P transistors are transistors of a second transistor type, such that the first, second, third, and fourth N transistors are first, second, third, and fourth transistors of the first transistor type, and such that the first, second, third, and fourth P transistors are first, second, third, and fourth transistors of the second transistor type, or b) the P transistors are transistors of a first transistor type and the N transistors are transistors of a second transistor type, such that the first, second, third, and fourth P transistors are first, second, third, and fourth transistors of the first transistor type, and such that the first, second, third, and fourth N transistors are first, second, third, and fourth transistors of the second transistor type;
• a layout of a first contact contacting the gate defining shape of the second transistor of the first transistor type;
• a layout of a second contact contacting the gate defining shape of the second transistor of the second transistor type;
• a layout of a third contact contacting the gate defining shape of the third transistor of the first transistor type;
• and
• a layout of a fourth contact contacting the gate defining shape of the third transistor of the second transistor type,
• wherein only one of the first and third contacts is positioned above and over the inner non-diffusion region.

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively;
• operating a computer to define at least six linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first direction, the at least six linear shapes spaced apart from each other in accordance with an integer multiple of a first pitch as measured in a second direction perpendicular to the first direction between lengthwise centerlines of the at least six linear shapes, wherein each linear shape within the gate layer region is spaced apart from at least one other linear shape by a lengthwise centerline-to-lengthwise centerline spacing as measured in the second direction that is substantially equal to the first pitch, and wherein all linear shapes within the gate layer region are within 1930 nanometers of each other, and
• wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including,
• (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor,
• (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that,
• (i) the first N and P transistors aligned along the first direction and electrically connected to each other through their gate defining shapes,
• (ii) the second N and P transistors aligned along the first direction and their gate defining shapes having extensions not electrically connected to each other,
• (iii) the third N and P transistors aligned along the first direction and their gate defining shapes having extensions not electrically connected to each other, and
• (iv) the fourth N and P transistors aligned along the first direction and electrically connected to each other through their gate defining shapes
• wherein either a) the N transistors are transistors of a first transistor type and the P transistors are transistors of a second transistor type, such that the first, second, third, and fourth N transistors are first, second, third, and fourth transistors of the first transistor type, and such that the first, second, third, and fourth P transistors are first, second, third, and fourth transistors of the second transistor type, or b) the P transistors are transistors of a first transistor type and the N transistors are transistors of a second transistor type, such that the first, second, third, and fourth P transistors are first, second, third, and fourth transistors of the first transistor type, and such that the first, second, third, and fourth N transistors are first, second, third, and fourth transistors of the second transistor type;
• operating a computer to define a first contact contacting the gate defining shape of the second transistor of the first transistor type;
• operating a computer to define a second contact contacting the gate defining shape of the second transistor of the second transistor type;
• operating a computer to define a third contact contacting the gate defining shape of the third transistor of the first transistor type;
• and
• operating a computer to define a fourth contact contacting the gate defining shape of the third transistor of the second transistor type,
• wherein only one of the first and third contacts is positioned above and over the inner non-diffusion region.