Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length

A computer readable medium having program instructions stored thereon for a semiconductor device layout, comprising:

• a layout of a first transistor of a first transistor type including a first gate electrode,
• a layout of a second transistor of the first transistor type including a second gate electrode,
• a layout of a third transistor of the first transistor type including a third gate electrode,
• a layout of a fourth transistor of the first transistor type including a fourth gate electrode,
• a layout of a first transistor of a second transistor type including a fifth gate electrode,
• a layout of a second transistor of the second transistor type including a sixth gate electrode,
• a layout of a third transistor of the second transistor type including a seventh gate electrode,
• a layout of a fourth transistor of the second transistor type including an eighth gate electrode,
• wherein both the first gate electrode and the fifth gate electrode extend lengthwise along a first line of extent in a first direction,
• wherein both the second gate electrode and the sixth gate electrode extend lengthwise along a second line of extent in the first direction,
• wherein both the third gate electrode and the seventh gate electrode extend lengthwise along a third line of extent in the first direction,
• wherein both the fourth gate electrode and the eighth gate electrode extend lengthwise along a fourth line of extent in the first direction,
• wherein the second line of extent in the first direction is separated from the first line of extent in the first direction by a first pitch distance as measured in a second direction perpendicular to the first direction,
• wherein the third line of extent in the first direction is separated from the second line of extent in the first direction by the first pitch distance as measured in the second direction,
• wherein the fourth line of extent in the first direction is separated from the third line of extent in the first direction by the first pitch distance as measured in the second direction,
• wherein the first gate electrode is formed to be in electrical connectivity with the fifth gate electrode, and wherein electrical connectivity between the first and fifth gate electrodes is provided by an electrical connection formed in a linear manner along the first line of extent in the first direction at a same level as the first and fifth gate electrodes,
• wherein the fourth gate electrode is formed to be in electrical connectivity with the eighth gate electrode, and wherein electrical connectivity between the fourth and eighth gate electrodes is provided by an electrical connection formed in a linear manner along the fourth line of extent in the first direction at a same level as the fourth and eighth gate electrodes,
• a first electrical connectivity layout feature defined to extend in a linear manner along the second line of extent in the first direction away from the second gate electrode and in an orientation of the first direction directed toward the sixth gate electrode;
• a second electrical connectivity layout feature defined to extend in a linear manner along the second line of extent away from the second gate electrode and in an orientation of the first direction directed away from the sixth gate electrode, the first electrical connectivity layout feature and the second electrical connectivity layout feature and the second gate electrode having a first combined length as measured in the first direction;
• a third electrical connectivity layout feature defined to extend in a linear manner along the third line of extent in the first direction away from the third gate electrode and in an orientation of the first direction directed toward the seventh gate electrode;
• a fourth electrical connectivity layout feature defined to extend in a linear manner along the third line of extent away from the third gate electrode and in an orientation of the first direction directed away from the seventh gate electrode, the third electrical connectivity layout feature and the fourth electrical connectivity layout feature and the third gate electrode having a second combined length as measured in the first direction, wherein the second combined length is greater than the first combined length;
• a fifth electrical connectivity layout feature defined to extend in a linear manner along the second line of extent in the first direction away from the sixth gate electrode and in an orientation of the first direction directed toward the second gate electrode;
• a sixth electrical connectivity layout feature defined to extend in a linear manner along the second line of extent away from the sixth gate electrode and in an orientation of the first direction directed away from the second gate electrode, the fifth electrical connectivity layout feature and the sixth electrical connectivity layout feature and the sixth gate electrode having a third combined length as measured in the first direction;
• a seventh electrical connectivity layout feature defined to extend in a linear manner along the third line of extent in the first direction away from the seventh gate electrode and in an orientation of the first direction directed toward the third gate electrode;
• and
• an eighth electrical connectivity layout feature defined to extend in a linear manner along the third line of extent away from the seventh gate electrode and in an orientation of the first direction directed away from the third gate electrode, the seventh electrical connectivity layout feature and the eighth electrical connectivity layout feature and the seventh gate electrode having a fourth combined length as measured in the first direction, wherein the third combined length is greater than the fourth combined length.