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US 8,253,454 B2Granted
Phase lock loop with phase interpolation by reference clock and method for the same
AssigneeRealtek Semiconductor Corp.
InventorChia-Liang Lin
Life of this patent
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Abstract
The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.
Claims17
A phase lock loop (PLL) comprising:
- a phase-interpolation controller for generating a phase-interpolation control signal from an input clock;
- a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference;
- a loop filter for filtering the phase error signal to generate a first control signal;
- a phase-interpolated oscillator for generating an output clock under a phase interpolation by a first reference clock controlled by the phase-interpolation control signal and an oscillation condition controlled by the first control signal;
- a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer;
- and
- a variable delay module, coupled to the phase/frequency detector, for delaying the input clock by an amount controlled by a second control signal to generate the second reference clock.
4 more elements
A phase lock loop (PLL) comprising:
- a phase-interpolation controller for generating a phase-interpolation control signal from an input clock;
- a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference;
- a loop filter for filtering the phase error signal to generate a first control signal;
- a phase-interpolated oscillator for generating an output clock under a phase interpolation by a first reference clock controlled by the phase-interpolation control signal and an oscillation condition controlled by the first control signal;
- a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer;
- and
- a fixed delay circuit, coupled to the phase-interpolated oscillator, for delaying the input clock to generate the first reference clock to the phase-interpolated oscillator.
4 more elements
A phase lock loop (PLL) comprising:
- a phase-interpolation controller for generating a phase-interpolation control signal from an input clock;
- a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference;
- a loop filter for filtering the phase error signal to generate a first control signal;
- a phase-interpolated oscillator for generating an output clock under a phase interpolation by a first reference clock controlled by the phase-interpolation control signal and an oscillation condition controlled by the first control signal;
- and
- a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer;
- wherein the phase-interpolation controller comprising:
- a flip-flop for receiving the input clock and outputting the phase-interpolation control signal;
- and
- an inverter chain for receiving the phase-interpolation control signal and outputting a reset signal to reset the flip-flop.
7 more elements
A method of phase locking comprising:
- generating a phase-interpolation control signal;
- detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference;
- filtering the phase error signal to generate a first control signal;
- generating an output clock under a phase interpolation controlled by the phase-interpolation control signal and an oscillation condition controlled by the first control signal;
- dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer;
- and
- delaying an input clock by a controlled amount by a second control signal to generate the second reference clock.
4 more elements
A method of phase locking comprising:
- generating a phase-interpolation control signal;
- detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference;
- filtering the phase error signal to generate a first control signal;
- generating an output clock under a phase interpolation controlled by the phase-interpolation control signal and an oscillation condition controlled by the first control signal;
- dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer;
- and
- delaying the input clock to generate a first reference clock.
4 more elements
Dependencies are inferred from the claim text.