Oscillation signal generator for compensating for I/Q mismatch and communication system including the same

An oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch, the oscillation signal generator comprising:

• a first latch configured to generate an I oscillation signal;
• a second latch that is cross-coupled with the first latch and generates a Q oscillation signal;
• and
• a phase compensator connected to at least one of the first latch or the second latch,
• wherein the first latch comprises:
• a first I differential transistor pair configured to operate in response to a clock signal;
• and
• a second I differential transistor pair configured to operate in response to a complementary clock signal,
• the phase compensator complementarily adjusts a bias current of the first I differential transistor pair and a bias current of the second I differential transistor pair, wherein the phase compensator comprises:
• a first offset current source that is connected to a first common node of the first I differential transistor pair and supplies a first offset current to the first common node;
• and
• a second offset current source that is connected to a second common node of the second I differential transistor pair and supplies a second offset current to the second common node.

A communication system comprising:

• an oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch, the oscillation signal generator comprising:
• a first latch configured to generate an I oscillation signal;
• a second latch that is cross-coupled with the first latch and generates a Q oscillation signal;
• and
• a phase compensator connected to at least one of the first latch or the second latch,
• wherein the first latch comprises:
• a first I differential transistor pair configured to operate in response to a clock signal;
• and
• a second I differential transistor pair configured to operate in response to a complementary clock signal,
• the phase compensator complementarily adjusts a bias current of the first I differential transistor pair and a bias current of the second I differential transistor pair;
• a local oscillator that is connected to the oscillation signal generator and generates an oscillation signal having a two times higher frequency than that of the I oscillation signal and the Q oscillation signal;
• and
• a phase mismatch detector configured to detect an amount of a phase mismatch between an I signal and a Q signal.

An oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch, the oscillation signal generator comprising:

• a first latch configured to generate an I oscillation signal;
• a second latch that is cross-coupled with the first latch and generates a Q oscillation signal;
• and
• a phase compensator connected to at least one of the first latch or the second latch, wherein the first latch comprises:
• a first I differential transistor pair configured to operate in response to a clock signal;
• and
• a second I differential transistor pair configured to operate in response to a complementary clock signal, and
• the phase compensator complementarily adjusts a bias current of the first I differential transistor pair and a bias current of the second I differential transistor pair, wherein the phase compensator further comprises:
• a third offset current source that is connected to a third common node of the first Q differential transistor pair and supplies a third offset current to the third common node;
• and
• a fourth offset current source that is connected to a fourth common node of the second Q differential transistor pair and supplies a fourth offset current to the fourth common node.

A communication system comprising:

• an oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch, the oscillation signal generator comprising:
• a first latch configured to generate an I oscillation signal;
• a second latch that is cross-coupled with the first latch and generates a Q oscillation signal;
• and
• a phase compensator connected to at least one of the first latch or the second latch, wherein the first latch comprises:
• a first I differential transistor pair configured to operate in response to a clock signal;
• and
• a second I differential transistor pair configured to operate in response to a complementary clock signal, and
• the phase compensator complementarily adjusts a bias current of the first I differential transistor pair and a bias current of the second I differential transistor pair;
• a local oscillator that is connected to the oscillation signal generator and generates an oscillation signal having a two times higher frequency than that of the I oscillation signal and the Q oscillation signal;
• and
• a phase mismatch detector configured to detect an amount of a phase mismatch between an I signal and a Q signal.