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US 8,247,849 B2Granted
Two-transistor pixel array
AssigneeLife Technologies Corporation
InventorsKeith Fife, Kim Johnson, Mark Milgrew
Life of this patent
Estimating the term…
Abstract
A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device.
Claims17
A device comprising:
- an array of pixels, at least some pixels in the array comprising:
- a chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer;
- and
- a second transistor including a first source/drain terminal, a second source/drain terminal and a gate terminal, wherein the first source/drain terminal of the second transistor is directly connected to the first source/drain terminal of the chemFET;
- and
- a plurality of pairs of lines coupled to pixels in the array, wherein each pair of lines includes a first line directly connected to second source/drain terminals of chemFETs of a corresponding first plurality of pixels in the array, and a second line directly connected to second source/drain terminals of second transistors of the corresponding first plurality of pixels in the array.
3 more elements
A device comprising:
- an array of pixels arranged in a plurality of rows and a plurality of columns, at least some pixels in the array comprising:
- a chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer;
- and
- a select transistor including a first source/drain terminal, a second source/drain terminal and a control gate terminal, wherein the first source/drain terminal of the select transistor is directly connected to the first source/drain terminal of the chemFET;
- a plurality of rows of lines coupled to pixels in the array, wherein a given row line in the plurality of row lines is directly connected to control gate terminals of select transistors of pixels arranged in a corresponding row in the plurality of rows;
- a plurality of sets of column lines coupled to pixels in the array, wherein a given set in the plurality of sets is coupled to a pair of adjacent pixels arranged in a given column in the plurality of columns, the given set including a first column line directly connected to the second source/drain terminal of the select transistor of a first pixel of the pair of adjacent pixels, a second column line directly connected to the second source/drain terminal of the select transistor of a second pixel of the pair of adjacent pixels, and a third column line directly connected to the second source/drain terminals of the chemFETs of the pair of adjacent pixels.
3 more elements
A device comprising:
- an array of pixels, a given pixel in the array of pixels comprising:
- a first chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal, a second source/drain terminal and a floating gate;
- and
- a second chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal, a second source/drain terminal and a floating gate;
- a plurality of row lines coupled to the array of pixels, wherein a given row line is directly connected to the first source/drain terminals of first and second chemFETs of the given pixel;
- a plurality of pairs of column lines coupled to the array of pixels, wherein a given pair of column lines includes a first line directly connected to the second source/drain terminal of the first chemFET of the given pixel, and a second column line directly connected to the second source/drain terminal of the second chemFET of the given pixel;
- and
- circuitry coupled to the row lines and the pairs of column lines to read the given pixel, the circuitry comprising:
- bias circuitry to apply a bias voltage to the given row line;
- and
- sense circuitry to read the given pixel based on a sampled voltage level on the first in the given pair, and further based on a sampled voltage level on the second column line in the given pair.
8 more elements
Dependencies are inferred from the claim text.