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US 8,238,173 B2Granted
Using storage cells to perform computation
AssigneeZikbit Ltd.
InventorsAvidan Akerib, Oren Agam, Eli Ehrman, Moshe Meyassed
Life of this patent
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Abstract
An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.
Claims6
A NOR device comprising:
- a plurality of memory cells which store data;
- and
- an activation unit to activate at least two of said memory cells in a column at time thereby to generate a NOR output of said data of said at least two memory cells, and wherein said activation unit comprises:
- a multiple row decoder to activate at least one cell in each of more than one row of said memory cells at a time;
- and
- an output unit at least to write the NOR'd output of at least one column of activated cells into said memory cells.
3 more elements
An in-memory processor comprising:
- a memory array which stores data;
- and
- an activation unit to activate at least two cells in a column of said memory array at the same time thereby to generate a Boolean function output of said data of said at least two cells, wherein said activation unit comprises:
- a multiple row decoder to activate at least one cell in each of more than one row of said memory array at a time;
- and an output unit at least to write the output of at least one column of said activated cells into said memory array, said output being said Boolean function of the said activated cells in each said column.
2 more elements
Dependencies are inferred from the claim text.