Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof

A memory array, comprising:

• a dielectric pillar;
• first and second separated semiconductor structures adjacent to the dielectric pillar and respectively wrapping around portions of the dielectric pillar;
• a first string of series-coupled first memory cells, each first memory cell comprising a first portion of a charge trap adjacent to the first semiconductor structure and a first control gate adjacent to the first portion of the charge trap;
• and
• a second string of series-coupled second memory cells, each second memory cell comprising a second portion of the charge trap adjacent to the second semiconductor structure and a second control gate adjacent to the second portion of the charge trap;
• wherein each of the first control gates is electrically isolated from each of the second control gates;
• and
• wherein the charge trap is wrapped completely around the dielectric pillar.

A method of forming a memory array, comprising:

• forming first and second semiconductor structures;
• forming a first portion of a charge storage structure adjacent to the first semiconductor structure and a second portion of the charge storage structure adjacent to the second semiconductor structure;
• forming first control gates adjacent to the first portion of the charge storage structure to form a first memory cell at each intersection of a first control gate and the first portion of the charge storage structure so that the first semiconductor structure couples the first memory cells in series to form a string of series-coupled first memory cells;
• forming second control gates adjacent to the second portion of the charge storage structure to form a second memory cell at each intersection of a second control gate and the second portion of the charge storage structure so that the second semiconductor structure couples the second memory cells in series to form a string of series-coupled second memory cells;
• wherein each first control gate is electrically isolated from each second control gate.

A method of forming a memory array, comprising:

• forming first and second dielectric pillars, each having respective separated first and second semiconductor structures adjacent thereto;
• forming a first string of series-coupled first memory cells adjacent to the first dielectric pillar using the respective adjacent first semiconductor structure;
• forming a second string of series-coupled first memory cells adjacent to the second dielectric pillar using the respective adjacent first semiconductor structure, wherein at least one first memory cell from the first string of series-coupled first memory cells and at least one first memory cell from the second string of series-coupled first memory cells are coupled to a first common access line;
• forming a first string of series-coupled second memory cells adjacent to the first dielectric pillar using the respective adjacent second semiconductor structure;
• and
• forming a second string of series-coupled second memory cells adjacent to the second dielectric pillar using the respective adjacent second semiconductor structure, wherein at least one second memory cell from the first string of series-coupled second memory cells and at least one second memory cell from the second string of series-coupled second memory cells are coupled to a second common access line that is electrically isolated from the first common access line.

A method of forming a memory array, comprising:

• forming alternating first and second dielectrics over a first semiconductor;
• forming an opening through the alternating first and second dielectrics;
• lining the opening with a second semiconductor;
• forming a dielectric pillar within the opening adjacent to the second semiconductor;
• removing a portion of the second semiconductor to form separated first and second semiconductor structures therefrom;
• forming a charge storage structure adjacent to the first and second semiconductor structures;
• forming a first and a second conductor respectively adjacent to first and second portions of the charge storage structure, the first and second conductors electrically isolated from each other, wherein the first conductor adjacent to the first portion of the charge storage structure defines a first memory cell and the second conductor adjacent to the second portion of the charge storage structure defines a second memory cell;
• forming a third and a fourth conductor respectively adjacent to third and fourth portions of the charge storage structure, the third and fourth conductors electrically isolated from each other, wherein the third conductor adjacent to the third portion of the charge storage structure defines a third memory cell and the fourth conductor adjacent to the fourth portion of the charge storage structure defines a fourth memory cell;
• wherein the first semiconductor structure couples the first and third memory cells in series and the second semiconductor structure couples the second and fourth memory cells in series.

A method of forming a memory array, comprising:

• forming alternating first and second dielectrics over a first semiconductor;
• forming a first opening through the alternating first and second dielectrics;
• lining the first opening with a second semiconductor;
• forming a third dielectric within the first opening adjacent to the second semiconductor;
• removing a portion of the second semiconductor;
• forming a second opening through the third dielectric that extends through remaining portions of the second semiconductor to form first and second dielectric pillars from the third dielectric and first and second separated semiconductor structures adjacent to the first dielectric pillar and first and second separated semiconductor structures adjacent to the second dielectric pillar;
• forming first and second portions of a first charge storage structure respectively adjacent to the separated first and second semiconductor structures adjacent to the first dielectric pillar and first and second portions of a second charge storage structure respectively adjacent to the separated first and second portions of the fourth semiconductor on the second dielectric pillar;
• and
• forming a conductor adjacent to the first portions of the first and second charge storage structures to respectively define first and second memory cells, where the conductor intersects the first portions of the first and second charge storage structures, that are commonly coupled to the conductor.