Interleaving scheme for an LDPC coded QPSK/8PSK system
AssigneeAvailink, Inc.
InventorsMing Yang, Juntan Zhang, Zhiyong Wu, Fengwen Sun
Life of this patent
Estimating the term…
Abstract
An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
Claims6
A digital communications transmitter interleaving LDPC encoded bits in a QPSK modulation system based on a rule:
- {
- b
- ~
- i
- =
- b
- i
- -
- i
-
-
- mod
-
-
- 256
- +
- (
- i
-
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 8
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 1
- =
- b
- (
- i
- +
- 1
- )
- -
- (
- i
- +
- 1
- )
-
-
- mod
-
-
- 256
- +
- (
- (
- i
-
- +
- 1
- )
-
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- +
- 1
- 8
- ⌋
-
- mod
-
-
- 32
- ,
- for
- iε{i|0≦i≦Nldpc—bits−1, and imod2=0}iε{i|0≦i≦Nldpc—bits−1, and imod2=0}, where └x┘ is the floor function which returns the largest integer that is less than or equal to x, Nldpc—bits=15360 is the codeword length of the LDPC code in use.
A digital communications receiver employing an LDPC decoder for decoding interleaved LDPC encoded bits in a QPSK modulation mode based on a rule:
- {
- b
- ~
- i
- =
- b
- i
- -
- i
-
-
- mod
-
-
- 256
- +
- (
- i
-
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 8
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 1
- =
- b
- (
- i
- +
- 1
- )
- -
- (
- i
- +
- 1
- )
-
-
- mod
-
-
- 256
- +
- (
- (
- i
-
- +
- 1
- )
-
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- +
- 1
- 8
- ⌋
-
- mod
-
-
- 32
- ,
- for iε{i|0≦i≦Nldpc—bits−1, and imod2=0}, where └x┘ is the floor function which returns the largest integer that is less than or equal to x, Nldpc—bits=15360 is the codeword length of the LDPC code in use.
A computer readable medium storing a computer program for performing a method specifying an interleaving scheme of LDPC encoded bits in a QPSK modulation system base on a rule:
- {
- b
- ~
- i
- =
- b
- i
- -
- i
-
-
- mod
-
-
- 256
- +
- (
- i
-
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 8
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 1
- =
- b
- (
- i
- +
- 1
- )
- -
- (
- i
- +
- 1
- )
-
-
- mod
-
-
- 256
- +
- (
- (
- i
-
- +
- 1
- )
-
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- +
- 1
- 8
- ⌋
-
- mod
-
-
- 32
- ,
- for iε{i|0≦i≦Nldpc—bits−1, and imod2=0}, where └x┘ is the floor function which returns the largest integer that is less than or equal to x, Nldpc—bits=15360 is the codeword length of the LDPC code in use.
A digital communications transmitter interleaving LDPC encoded bits in a 8PSK modulation system based on a rule:
- {
- b
- ~
- i
- =
- b
- (
- 8
- ×
- ⌊
- i
- 768
- ⌋
- +
- N
- offset
- +
- i
- 3
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 1
- =
- b
- (
- 8
- ×
- ⌊
- i
- 768
- ⌋
- +
- N
- offset
- +
- i
- 3
-
- mod
-
-
- 8
- +
- 160
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 2
- =
- b
- (
- i
- 3
- +
- 32
- ×
- N
- offset
- +
- 10240
- )
-
- mod
-
-
- N
- idpc
-
- _
-
- bits
- -
- (
- i
- 3
- )
-
- mod
-
-
- 256
- +
- (
- i
- 3
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- for iε{i|0≦i≦Nldpc—bits−1, and imod3=0}, where └x┘ is the floor function which returns the largest integer that is less than or equal to x, Nldpc—bits=15360 is the codeword length of the LDPC code in use, and the offset values NOffset for different code rates are defined as:
- Rate
- NOffset
- 3/5
- 40
- 2/3
- 40
- 3/4
- 80
- 5/6
- 88
- 13/15
- 104
- 9/10
- 160.
A digital communications receiver employing an LDPC decoder for decoding interleaved LDPC encoded bits in a 8PSK modulation system based on a rule:
- {
- b
- ~
- i
- =
- b
- (
- 8
- ×
- ⌊
- i
- 768
- ⌋
- +
- N
- offset
- +
- i
- 3
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 1
- =
- b
- (
- 8
- ×
- ⌊
- i
- 768
- ⌋
- +
- N
- offset
- +
- i
- 3
-
- mod
-
-
- 8
- +
- 160
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 2
- =
- b
- (
- i
- 3
- +
- 32
- ×
- N
- offset
- +
- 10240
- )
-
- mod
-
-
- N
- idpc
-
- _
-
- bits
- -
- (
- i
- 3
- )
-
- mod
-
-
- 256
- +
- (
- i
- 3
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- for iε{i|0≦i≦Nldpc—bits−1, and imod3=0}, where └x┘ is the floor function which returns the largest integer that is less than or equal to x, Nldpc—bits=15360 is the codeword length of the LDPC code in use, and the offset values NOffset for different code rates are defined as:
- Rate
- NOffset
- 3/5
- 40
- 2/3
- 40
- 3/4
- 80
- 5/6
- 88
- 13/15
- 104
- 9/10
- 160.
A computer readable medium storing a computer program for performing a method specifying an interleaving scheme of LDPC encoded bits in an 8PSK modulation system base on a rule:
- {
- b
- ~
- i
- =
- b
- (
- 8
- ×
- ⌊
- i
- 768
- ⌋
- +
- N
- offset
- +
- i
- 3
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 1
- =
- b
- (
- 8
- ×
- ⌊
- i
- 768
- ⌋
- +
- N
- offset
- +
- i
- 3
-
- mod
-
-
- 8
- +
- 160
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- b
- ~
- i
- +
- 2
- =
- b
- (
- i
- 3
- +
- 32
- ×
- N
- offset
- +
- 10240
- )
-
- mod
-
-
- N
- idpc
-
- _
-
- bits
- -
- (
- i
- 3
- )
-
- mod
-
-
- 256
- +
- (
- i
- 3
-
- mod
-
-
- 8
- )
- ×
- 32
- +
- ⌊
- i
- 24
- ⌋
-
- mod
-
-
- 32
- for iε{i|0≦i≦Nldpc—bits−1, and imod3=0}, where └x┘ is the floor function which returns the largest integer that is less than or equal to x, Nldpc—bits=15360 is the codeword length of the LDPC code in use, and the offset values NOffset for different code rates are defined as:
- Rate
- NOffset
- 3/5
- 40
- 2/3
- 40
- 3/4
- 80
- 5/6
- 88
- 13/15
- 104
- 9/10
- 160.
Dependencies are inferred from the claim text.