Methods for defining contact grid in dynamic array architecture

A method for optimizing a cell layout, comprising:

• defining a first virtual grate as a set of parallel virtual lines of uniform pitch extending across the cell layout in a first direction;
• defining a second virtual grate as a set of parallel virtual lines of uniform pitch extending across the cell layout in a second direction that is perpendicular to the first direction, wherein each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid;
• for either the first virtual grate, the second virtual grate, or both the first and second virtual grates, defining a respective lower pitch limit, a respective upper pitch limit, and a respective pitch increment value, wherein a pitch range for a given virtual grate extends from the lower pitch limit of the given virtual grate to the upper pitch limit of the given virtual grate in increments of the pitch increment value of the given virtual grate;
• operating a computer to define a number of variants of the vertical connection placement grid, wherein each variant of the vertical connection placement grid corresponds to a different combination of first and second virtual grate pitch values within their respective pitch ranges;
• operating the computer to generate multiple layouts of a cell, wherein each of the multiple layouts of the cell is generated using a different variant of the vertical connection placement grid;
• operating the computer to calculate for each of the multiple layouts of the cell an area efficiency metric and a manufacturability rating metric;
• evaluating the area efficiency metric and manufacturability rating metric for the multiple layouts of the cell to determine an optimum vertical connection placement grid;
• and
• operating the computer to record on a computer readable storage medium the layout of the cell using the optimum vertical connection placement grid.

A semiconductor chip, comprising:

• a cell defined to include a number of vertical connection structures placed in accordance with a vertical connection placement grid,
• wherein the vertical connection placement grid is defined by a first virtual grate and a second virtual grate, the first virtual grate defined by a set of parallel virtual lines extending across a layout of the cell in a first direction, the second virtual grate defined by a set of parallel virtual lines extending across the layout of the cell in a second direction substantially perpendicular to the first direction, wherein each intersection point between virtual lines of the first and second virtual grates is a gridpoint within the vertical connection placement grid,
• wherein the virtual lines of the first virtual grate correspond to potential placement locations for layout features in a particular chip level,
• wherein the virtual lines of the second virtual grate correspond to potential placement locations for layout features in another chip level different than the particular chip level associated with the first virtual grate,
• wherein vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the chip levels associated with the first and second virtual grates, and
• wherein the vertical connection structures are placed so as to minimize a number of different vertical connection structure edge-to-edge spacing sizes between neighboring vertical connection structures across the layout of the cell and so as to minimize a layout area of the cell.