Semiconductor memory device adopting improved local input/output line precharging scheme

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including at least one access transistor and one storage capacitor;
• a plurality of first sense amplifiers electrically connected to corresponding bit lines electrically connected to the plurality of memory cells;
• a plurality of precharging units each of which includes a first conductive type precharging unit, a second conductive type precharging unit, an equalizing unit, a delay unit and a NAND gate,
• the first conductive type precharging unit configured to precharge first input/output lines,
• the equalizing unit configured to equalize a voltage of the first input/output lines,
• the second conductive type precharging unit configured to precharge the first input/output lines following an elapsed time after an associated first sense amplifier of the plurality of first sense amplifiers is activated and while an associated column selecting unit of a plurality of column selecting units is deactivated,
• the delay unit configured to delay an enable signal to a corresponding sense amplifier of a plurality of second sense amplifiers,
• the NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the equalizing unit, to produce a NAND response in order to activate the second conductive type precharging unit.

A read data path circuit of a semiconductor memory device, the circuit comprising:

• a first sense amplifier;
• a second sense amplifier;
• a column selecting unit configured to operationally connect bit lines corresponding to the first sense amplifier to input/output lines corresponding to the second sense amplifier, in response to a selection signal;
• a precharging unit configured to precharge the input/output lines by NMOS transistors, the precharging unit configured to equalize a voltage of the input/output lines by a PMOS transistor, and the precharging unit configured to precharge the input/output lines by PMOS transistors following an elapsed time after the first sense amplifier is activated and the selection signal is deactivated, the precharging unit including
• a delay unit configured to delay an enable signal to the second sense amplifier;
• and
• a NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the PMOS transistor for equalizing, to produce a NAND response in order to activate the second conductive type precharging unit.