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US 8,222,920 B2Granted
Dynamic phase alignment
AssigneeMeta Systems
InventorJean Barbier
Life of this patent
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Abstract
Embodiments of the present disclosure provide methods and integrate circuits with dynamic phase alignment between an input data signal and a clock signal. In some embodiments, a sampling window of the input data signal may be determined and timing of the input data signal may be adjusted to enable the input data signal to be sampled within the sampling window. Other embodiments may be disclosed and claimed.
Claims16
A method for sampling an input data signal by an integrated circuit (IC), the method comprising:
- receiving, by an input terminal of the IC, the input data signal;
- routing the input data signal, via a delay chain of the IC, to a sampling circuit of the IC to sample the input data signal using a clock signal;
- and
- dynamically adjusting timing of the input data signal to enable the input data signal to be sampled by the sampling circuit within a sampling window of the input data signal without modifying the clock signal;
- wherein a sampling window is a time period where the input data signal is stable for sampling.
2 more elements
An Integrated Circuit (IC), comprising:
- an input terminal, configured to receive an input data signal;
- a delay chain, coupled with the input terminal, configured to receive the input data signal, adjust timing of the received input data signal by a configurable amount of delay, and output the timing adjusted input data signal;
- and
- a sampling circuit, coupled with output of the delay chain, configured to sample the timing adjusted input data signal within a sampling window, using a clock signal, wherein said sampling within the sampling window is enabled in part by said adjusting of timing of the input data signal by the delay chain.
1 more element
A reconfigurable circuit comprising:
- a plurality of reconfigurable function blocks;
- and
- a dynamic phase alignment circuit, including:
- an input terminal, configured to receive an input data signal;
- a delay chain, coupled with the input terminal, configured to receive the input data signal, adjust timing of the received input data signal by a configurable amount of delay, and output the timing adjusted input data signal;
- and
- a sampling circuit, coupled with output of the delay chain, configured to sample the timing adjusted input data signal within a sampling window, using a clock signal, wherein said sampling with the sampling window is enabled in part by said adjusting of timing of the input data signal by the delay chain.
4 more elements
Dependencies are inferred from the claim text.