# US 8,218,369 B2 · Non-volatile memory low voltage and high speed erasure method

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- Number: US 8,218,369 B2
- Document ID: US8218369B2
- Status: Granted
- Kind: B2
- Application number: 12/692,868
- Filed: 2010-01-25
- Published: 2011-07-28
- Granted: 2012-07-10
- Earliest claimed: 2010-01-25
- Assignees: Yield Microelectronics Corp.
- Inventors: Hsin Chang Lin; Wen-Chien Huang
- Web page: https://patentgrep.com/patent/US8218369B2

## CPC

- H10D 30/685: {from the channel}
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.

## Claims

### Claim 1

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising: a stacked gate structure disposed on a P-type semiconductor substrate, a source and a drain disposed on two sides of said stacked gate structure and in said P-type semiconductor substrate, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
applying a substrate voltage Vsub, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said P-type semiconductor substrate, said source, said drain, and said control gate, when Vsub is a ground voltage (=0), while satisfying following conditions:
a. Vd>5V, Vs is close to or equal to 0; and
b. Vd>Vc≧0, Vc decrementing with erasure time; and
when Vsub is a negative voltage, while satisfying following conditions:
a. Vs is close to or equal to Vsub; and
b. Vd>Vc, Vc decrementing with erasure time.

### Claim 2

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising: a P-type well disposed in an N-type semiconductor substrate, a stacked gate structure disposed on said P-type well, a source and a drain disposed on two sides of said stacked gate structure and in said P-type well, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
applying a substrate voltage Vsub, a P-type well voltage Vpwell, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said N-type semiconductor substrate, said P-type well, said source, said drain, and said control gate, when Vpwell is a ground voltage (=0), while satisfying following conditions:
a. Vd>5V, Vs is close to or equal to 0; and
b. Vd>Vc≧0, Vc decrementing with erasure time; and
when Vpwell is a negative voltage, while satisfying following conditions:
a. Vs is close to or equal to Vpwell; and
b. Vd>Vc, Vc decrementing with erasure time.

### Claim 3

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising: a stacked gate structure disposed on an N-type semiconductor substrate, a source and a drain disposed on two sides of said stacked gate structure and in said N-type semiconductor substrate, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
applying a substrate voltage Vsub, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said N-type semiconductor substrate, said source, said drain, and said control gate, while satisfying following conditions:
a. Vsub and Vs>5V;
b. Vd is close to or equal to 0; and
c. Vc>Vd, Vc incrementing with erasure time.

### Claim 4

A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising: an N-type well disposed in a P-type semiconductor substrate, a stacked gate structure disposed on said N-type well, a source and a drain disposed on two sides of said stacked gate structure and in said N-type well, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of:
applying a substrate voltage Vsub, an N-type well voltage Vnwell, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc on said P-type semiconductor substrate, said N-type well, said source, said drain, and said control gate, while satisfying following conditions:
a. Vnwell, and Vs>5V;
b. Vnwell≧Vs;
c. Vd is close to or equal to 0; and
d. Vnwell≧Vc>Vd, Vc incrementing with erasure time.