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US 8,213,244 B2Granted
Distributed write data drivers for burst access memories
AssigneeRound Rock Research, LLC
InventorsTodd A. Merritt, Troy A. Manning
Life of this patent
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Abstract
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.
Claims10
A method comprising:
- requesting the system to enter read mode;
- providing a random access memory device having a pinout comprising a /RAS (row address strobe) input pin, a /CAS (column address strobe) input pin, a /WE (write enable) input pin, eight or more address input pins, two or more data output pins, and a /OE (output enable) input pin;
- asserting an equilibrate signal to an equilibration device to equilibrate data lines of the memory device;
- performing a burst mode access of the memory device;
- and
- latching only one read-write control signal for the burst mode access.
3 more elements
Dependencies are inferred from the claim text.