# US 8,208,287 B2 · Contemporaneous margin verification and memory access for memory cells in cross-point memory arrays

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- Number: US 8,208,287 B2
- Document ID: US8208287B2
- Status: Granted
- Kind: B2
- Application number: 13/181,438
- Filed: 2011-07-12
- Published: 2011-11-03
- Granted: 2012-06-26
- Earliest claimed: 2008-09-19
- Assignees: Unity Semiconductor Corporation
- Inventors: Christophe Chevallier; Chang Hua Siau
- Web page: https://patentgrep.com/patent/US8208287B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2211/5634: Reference cells
- G11C 2211/5646: Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
- G11C 2213/71: Three dimensional array
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

## Claims

### Claim 1

An integrated circuit, comprising:
a silicon semiconductor substrate including active circuitry fabricated on the silicon semiconductor substrate;
at least one memory layer fabricated directly above and in contact with the silicon semiconductor substrate; and
at least one two-terminal cross-point memory array disposed in each memory layer, each array including a plurality of re-writeable non-volatile two-terminal memory elements, each memory element operative to store data as a plurality of conductivity profiles and configured to retain the data in the absence of electrical power, each array is electrically coupled with the active circuitry, and the active circuitry including
a memory access circuit configured to select at least one of the memory elements for a read operation,
a sensing circuit configured to sense a reference signal and a leakage signal during a first cycle of the read operation and to sense a read current from selected memory elements and the leakage signal during a second cycle of the read operation, the sensing circuit operative to generate a data signal indicative of stored data in selected memory elements, and
a margin manager circuit configured to manage a read margin for selected memory elements substantially during the first and second cycles and operative to determine if a value of the stored data in selected memory elements is within a specified level of the read margin.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the margin manager circuit further comprises a margin restoration circuit configured to re-write the value of the stored data to the selected memory elements to restore the read margin to the specified level of the read margin.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein each memory element includes an electrolytic tunnel barrier in contact with and electrically in series with a mixed valence conductive oxide that includes mobile oxygen ions.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein each memory element includes an electrolytic tunnel barrier in contact with and electrically in series with a conductive metal oxide (CMO) that includes mobile oxygen ions.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the margin manager circuit is further configured to determine that the value of the stored data is associated with a first range of resistance values that specify the read margin for the selected memory elements.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the first range of resistance values are indicative of a hard state for the stored data.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the hard state comprises
a hard programmed state for the stored data if the data signal from the sensing circuit is indicative of a value of zero, or
a hard erased state for the stored data if the data signal from the sensing circuit is indicative of a value of one.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the margin manager circuit is further configured to determine that the value of the stored data is associated with a second range of resistance values that specify the read margin for the selected memory elements.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the second range of resistance values are indicative of a soft state for the stored data.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the soft state comprises
a soft programmed state for the stored data if the data signal from the sensing circuit is indicative of a value of zero, or
a soft erased state for the stored data if the data signal from the sensing circuit is indicative of a value of one.

### Claim 11 (depends on 8)

The integrated circuit of claim 8, wherein the margin manager circuit is operative to restore the read margin for selected memory elements by changing an association of the selected memory elements from the second range of resistance values to a first range of resistance values.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, wherein the margin manager circuit is operative to manage the read margin as a function of time.

### Claim 13 (depends on 1)

The integrated circuit of claim 1 and further comprising:
a capacitance element electrically coupled with the sensing circuit, and
the margin manager circuit is further configured, during the second cycle, to determine a rate of current flow to or from the capacitance element, the rate of current flow is indicative of whether the read margin for selected memory elements is associated with a specified level of read margin.

### Claim 14 (depends on 1)

The integrated circuit of claim 1, wherein the sensing circuit further comprises
a sense amplifier including an input and an output, and
a capacitor including a first node electrically coupled with the input and a second node electrically coupled with a first potential.

### Claim 15 (depends on 14)

The integrated circuit of claim 14 and further comprising:
a two-terminal non-volatile reference memory element operative to generate the reference signal in response to a reference voltage applied across first and second terminals of the reference memory element;
a first switch in electrical communication with the margin manager circuit and operative to electrically couple the first terminal of the reference memory element with the first node of the capacitor in response to a first signal activated by the margin manager circuit; and
a second switch in electrical communication with the margin manager circuit and operative to electrically couple the second terminal of a selected memory element with the first node of the capacitor in response to a second signal activated by the margin manager circuit, and
the margin manager circuit is operative to activate the first switch during the first cycle of the read operation to charge the capacitor and to activate the second switch during the second cycle of the read operation to discharge the capacitor.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the margin manager circuit further comprises a margin detector configured to activate the sense amplifier to sense a difference between the reference signal and the data signal, and
the margin detector is configured to activate the sense amplifier a plurality of times during the second cycle to sense the difference between the reference signal and the data signal.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the margin detector is configured to determine whether the read margin for the selected memory element is within the specified level of the read margin based on a magnitude of the difference between the reference signal and the data signal.

### Claim 18 (depends on 1)

The integrated circuit of claim 1, wherein the reference signal comprises a reference current.

### Claim 19 (depends on 1)

The integrated circuit of claim 1, wherein the leakage signal comprises leakage currents generated by a subset of the plurality of re-writeable non-volatile two-terminal memory elements that are not selected for the read operation.

### Claim 20 (depends on 1)

The integrated circuit of claim 1, wherein each memory element is configured to store at least two-bits of data and the margin manager circuit is configured to manage read margins for multi-level cells (MLC).

### Claim 21 (depends on 20)

The integrated circuit of claim 20 and further comprising:
a capacitive element; and
a sense amplifier included in the sensing circuit,
a first signal is triggered during the first cycle and is operative to charge the capacitive element, a second signal is triggered during the second cycle and is operative to discharge the capacitive element, and after the second signal is triggered, a plurality of sampling signals are sequentially timed to activate the sense amplifier at specific points in time while the capacitive element is discharging to capture margin samples and read samples, and the specific points in time are temporally positioned about a predetermined time point during the discharging.

### Claim 22 (depends on 21)

The integrated circuit of claim 21 and further comprising: a state table included in the at least one two-terminal cross-point memory array and operative to store the margin samples and the read samples that are captured during the specific points in time.

### Claim 23 (depends on 1)

The integrated circuit of claim 1 and further comprising: a capacitance element electrically coupled with the sensing circuit.

### Claim 24 (depends on 23)

The integrated circuit of claim 23, wherein the capacitive element comprises a sub-set of a plurality of conductive array lines in the at least one two-terminal cross-point memory array.

### Claim 25 (depends on 23)

The integrated circuit of claim 23, wherein the capacitive element comprises a capacitance of one or more of the plurality of re-writeable non-volatile two-terminal memory elements.

### Claim 26 (depends on 23)

The integrated circuit of claim 23, wherein the capacitive element comprises at least one two-terminal non-volatile reference memory element disposed in the at least one two-terminal cross-point memory array.

### Claim 27 (depends on 1)

The integrated circuit of claim 1, wherein each array includes a plurality of first conductive array lines and a plurality of second conductive array lines, each memory element is positioned between a cross-point of a unique pair of the plurality of first and second conductive array lines, each memory element includes a first terminal directly electrically coupled with its respective first conductive array line and a second terminal directly electrically coupled with its respective second conductive array line, and each memory element is directly electrically in series with its respective first and second conductive array lines.