Integrated circuit self aligned 3D memory array and manufacturing method

A memory device, comprising:

• an integrated circuit substrate;
• a plurality of stacks of conductive strips, the stacks being ridge-shaped and including at least two conductive strips separated by insulating material;
• a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and conductive lines;
• a layer of programmable resistive memory material between the plurality of conductive lines and the plurality of stacks, which establishes a 3D array of memory cells accessible via the plurality of conductive strips and the plurality of conductive lines;
• a row decoder coupled to the plurality of conductive lines;
• and
• a plane and column decoder coupled to the conductive strips in the plurality of stacks.

A memory device, comprising:

• an integrated circuit substrate;
• a plurality of stacks of semiconductor strips, the stacks being ridge-shaped and including at least two semiconductor strips separated by insulating material;
• a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the plurality of stacks and conductive lines;
• charge trapping structures in the interface regions between the plurality of conductive lines and the side surfaces of the semiconductor strips on the plurality of stacks, which establishes a 3D NAND array of charge trapping memory transistors accessible via the plurality of semiconductor strips and the plurality of conductive lines.

A memory device, comprising:

• an integrated circuit substrate;
• a plurality of stacks of n-type semiconductor strips, the stacks being ridge-shaped and including at least two semiconductor strips separated by insulating material;
• a plurality of p-type semiconductor lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the plurality of stacks and the plurality of p-type semiconductor lines;
• charge trapping structures in the interface regions between the plurality of conductive lines and the side surfaces of the semiconductor strips on the plurality of stacks, which establishes a 3D NAND array of charge trapping memory transistors accessible via the plurality of semiconductor strips and the plurality of conductive lines, the charge trapping structures including a tunneling dielectric structure including a composite of materials to establish an inverted U-shaped valence band energy level, a charge trapping layer and a blocking layer.

A method for manufacturing a memory device, comprising:

• forming a plurality of layers of a first conductive material separated by insulating material, on an integrated circuit substrate;
• etching the plurality of layers to define a plurality of stacks of conductive strips, the stacks being ridge-shaped and including at least two conductive strips separated by insulating material;
• forming a memory layer on sides of conductive strips in the plurality of stacks, the memory layer contacting side surfaces of the plurality of conductive strips;
• forming a layer of a second conductive material over and having a surface conformal with the memory layer on the plurality of stacks;
• and
• etching the layer of second conductive material to define a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the memory layer on the plurality of stacks, defining a 3D array of memory cells in interface regions at cross-points between side surfaces of the conductive strips on the stacks and conductive lines.