Low-H plasma treatment with N2 anneal for electronic memory devices
AssigneeSpansion LLC
InventorsAlexander H. Nickel, Allen L. Evans, Minh Quoc Tran, Lu You, Minh Van Ngo, Pei-Yuan Gao, William S. Brennan, Erik Wilson, Sung Jin Kim, Hieu Trung Pham
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Abstract
A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
Claims9
A method for forming a single damascene and/or dual damascene contact and interconnect structure, comprising:
- forming a copper layer in an opening in an insulating layer overlying a semiconductor body;
- annealing the copper layer;
- performing planarization of the copper layer, thereby making a top surface of a resultant copper feature flush with a top surface of the insulating layer;
- performing an in-situ low-H NH3 plasma treatment after the planarization of the copper layer;
- forming a low Si—H SiN etch stop layer over the copper feature and the insulating layer, wherein the SiN etch stop layer has a percentage of Si—H less than 0.20%.
Dependencies are inferred from the claim text.