Frequency corrector and clocking apparatus using the same

A clocking apparatus comprising a frequency corrector which comprises:

• a counter operative in response to a clock signal input at a first clock frequency for counting a number of clock pulses of the clock signal to divide the clock signal into a fraction of a natural number larger than unity to generate a signal at a second clock frequency, and for correcting a number of clock pulses of the signal at the second clock frequency in response to a correction signal to output a first frequency-divided signal;
• a frequency divider circuit that divides the first frequency-divided signal to output a unit time signal at a predetermined clock frequency and a second frequency-divided signal including a plurality of clock frequencies;
• a correction timing generator that decodes the first frequency-divided signal and the second frequency-divided signal to detect a correction timing for the first frequency-divided signal, and generates a plurality of correction timing signals different in timing from each other to output the plurality of correction timing signals;
• and
• a correction signal generator that generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to said counter,
• said apparatus further comprising:
• a clocking counter that generates clock time data in response to the unit time signal output from said frequency divider circuit to output the clock time data;
• and
• an operational circuit operative at a predetermined time interval for finding an error between reference clock time data and the clock time data, and for calculating the correction values on a basis of the error and the predetermined time interval to provide the correction values to said correction signal generator.

A clocking apparatus comprising a frequency corrector which comprises:

• a counter operative in response to a clock signal input at a first clock frequency for counting a number of clock pulses of the clock signal to divide the clock signal into a fraction of a natural number larger than unity to generate a signal at a second clock frequency, and for correcting a number of clock pulses of the signal at the second clock frequency in response to a correction signal to output a first frequency-divided signal;
• a frequency divider circuit that divides the first frequency-divided signal to output a unit time signal at a predetermined clock frequency and a second frequency-divided signal including a plurality of clock frequencies;
• a correction timing generator that decodes the first frequency-divided signal and the second frequency-divided signal to detect a correction timing for the first frequency-divided signal, and generates a plurality of correction timing signals different in timing from each other to output the plurality of correction timing signals;
• and
• a correction signal generator that generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to said counter,
• said apparatus further comprising:
• a clocking counter that generates clock time data in response to the unit time signal output from said frequency divider circuit to output the clock time data;
• an operational circuit operative at a specific time interval resultant from subtracting previous reference clock time data from new reference clock time data for finding an error between the new reference clock time data and the clock time data, and for calculating the correction values on the basis of the error and the specific time interval to provide the correction values to said correction signal generator;
• and
• a clock time data storage circuit for storing the new reference clock time data every time said operational circuit calculates the error and the correction values, and for providing the stored previous reference clock time data to said operational circuit.