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US 8,200,949 B1Granted
Policy based allocation of register file cache to threads in multi-threaded processor
AssigneeNVIDIA Corporation
InventorsDavid Tarjan, Kevin Skadron
Life of this patent
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Abstract
A multi-threaded processor system, method, and computer program product capable of utilizing a register file cache are provided for simultaneously processing a plurality of threads. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a register file and a register file cache in communication with the register file.
Claims20
An apparatus, comprising:
- a processor capable of simultaneously processing a plurality of threads, the processor including:
- a register file, and
- a register file cache in communication with the register file;
- wherein the processor is operable to:
- store first data in the register file cache or bypass the register file cache and write to the register file, copy the first data from the register file cache to the register file, retrieve the first data from the register file, store second data in the register file cache, retrieve the second data from the register file cache, and delete the second data from the register file cache before the second data is copied from the register file cache to the register file;
- wherein the register file cache is simultaneously utilized by each of the plurality of threads;
- wherein the register file cache is allocated amongst each of the plurality of threads based on a policy that dictates a number of registers of the register file cache that are allocated to each of the plurality of threads.
4 more elements
A computer program product embodied on a computer readable medium, comprising:
- computer code for processing a plurality of threads utilizing a processor including a register file and a register file cache in communication with the register file;
- wherein the processor is operable to:
- store first data in the register file cache or bypass the register file cache and write to the register file, copy the first data from the register file cache to the register file, retrieve the first data from the register file, store second data in the register file cache, retrieve the second data from the register file cache, and delete the second data from the register file cache before the second data is copied from the register file cache to the register file;
- wherein the register file cache is simultaneously utilized by each of the plurality of threads;
- wherein the register file cache is allocated amongst each of the plurality of threads based on a policy that dictates a number of registers of the register file cache that are allocated to each of the plurality of threads.
2 more elements
A method, comprising:
- processing a plurality of threads utilizing a processor including a register file and a register file cache in communication with the register file;
- wherein the processor is operable to:
- store first data in the register file cache or bypass the register file cache and write to the register file, copy the first data from the register file cache to the register file, retrieve the first data from the register file, store second data in the register file cache, retrieve the second data from the register file cache, and delete the second data from the register file cache before the second data is copied from the register file cache to the register file;
- wherein the register file cache is simultaneously utilized by each of the plurality of threads;
- wherein the register file cache is allocated amongst each of the plurality of threads based on a policy that dictates a number of registers of the register file cache that are allocated to each of the plurality of threads.
2 more elements
Dependencies are inferred from the claim text.