Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture

A method of operating a re-programmable non-volatile memory system, comprising:

• utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having x, y and z-directions and which comprises:
• a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate;
• a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x and columns in the y-directions;
• a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across the individual planes;
• a plurality of re-programmable non-volatile memory elements individually connected between the local bit lines and the word lines adjacent the crossings thereof at the plurality of locations;
• and wherein:
• a column of local bit lines in the y-direction is switchably accessed by a corresponding global bit line pair;
• individual local bit lines of even number in the column are switchably coupled to one designated line of the corresponding global bit line pair;
• and
• individual local bit lines of odd number in the column are switchably coupled to another designated line of the corresponding global bit line pair;
• a first plurality of select devices arranged to individually couple a selected row of local bit lines to a first designated lines of corresponding global bit line pairs in response to a select control signal;
• a second plurality of select devices arranged to individually couple an adjacent row of local bit lines to a second designated lines of corresponding global bit lines pairs in response to the select control signal;
• applying the select control signal to the first plurality of select devices in order to connect the selected row of local bit lines to the first designated lines of corresponding global bit line pairs;
• applying the select control signal to the second plurality of select devices in order to connect the adjacent row of local bit lines to the second designated lines of corresponding global bit line pairs;
• and
• causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected.