System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations

A computing device for performing data-parallel operations and task-parallel operations, comprising:

• a processing subsystem having a first switch fabric node (SFN) that includes:
• a first lane processing engine (LPE) having a first set of lane processing units (LPUs) configured to perform data-parallel operations, wherein in-order scheduling is implemented across the first set of LPUs, each LPU within the first set of LPUs performs a set of operations, each LPU within the first set of LPUs uses a different set of data for the set of operations, and the first set of LPUs accesses a first set of shared memory units (SMUs) via a first LPU interconnect;
• and
• a second LPE having a second set of LPUs configured to perform task-parallel operations, wherein in-order scheduling is implemented across the second set of LPUs, each LPU within the second set of LPUs performs a different set of operations, and the second set of LPUs accesses a second set of SMUs via a second LPU interconnect;
• and
• a system memory storing a processing control engine (PCE) configured to distribute instructions and data to the first LPE and the second LPE, wherein the instructions and data are associated with the data-parallel operations and the task-parallel operations as the case may be, wherein the PCE is further configured to:
• cause a first data movement unit (DMU) associated with the first LPE to transmit a first instruction set and multiple data sets to the first set of SMUs;
• and
• cause a second DMU associated with the second LPE to transmit multiple instruction sets to the second set of SMUs.

A computer-readable medium storing instructions, that when executed by a processor, cause a processor to perform data-parallel operations and task-parallel operations, by performing the steps of:

• configuring a first lane processing engine (LPE) having a first set of lane processing units (LPUs) to execute data-parallel operations, wherein in-order scheduling is implemented across the first set of LPUs, each LPU within the first set of LPUs performs a set of operations, and each LPU within the first set of LPUs uses a different set of data for the set of operations;
• configuring a second LPE having a second set of LPUs to execute task-parallel operations, wherein in-order scheduling is implemented across the second set of LPUs, and each LPU within the second set of LPUs performs a different set of operations;
• causing a first data movement engine (DMU) associated with the first LPE to retrieve a first instruction set associated with the data-parallel operations from an external memory unit (EMU) and to store the first instruction set in a first set of shared memory units (SMUs) associated with the first LPE;
• causing a second DMU associated with the second LPE to retrieve multiple instruction sets from one or more EMUs and to store the multiple instruction sets associated with the task-parallel operations in a second set of SMUs associated with the second LPE;
• causing each LPU in the first set of LPUs to copy the first instruction set from one of the SMUs included in the first set of SMUs into a private cache associated with the LPU;
• and
• causing each LPU in the second set of LPUs to copy one of the multiple instruction sets from one of the SMUs included in the second set of SMUs into a private cache associated with the LPU.