Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell

A resistive-change memory cell comprising:

• a first control transistor formed on a first substrate and having a source, gate, and drain;
• a second substrate formed on the first control transistor;
• a second control transistor formed on the second substrate and having a source, gate, and drain;
• and
• a variable resistance device connected to one of the source and the drain of the second control transistor and formed of a resistive-change memory, wherein:
• the source of the first control transistor is electrically connected to the source of the second control transistor,
• the drain of the first control transistor is electrically connected to the drain of the second control transistor, and
• the gate of the first control transistor is electrically connected to the gate of the second control transistor.

A method of fabricating a resistive-change memory cell, comprising:

• forming a first control transistor having a source, gate, and drain on a first substrate;
• forming a second substrate on the first control transistor;
• forming a second control transistor having a source, gate, and drain on the second substrate;
• and
• connecting a variable resistance device to one of the source and the drain of the second control transistor, the variable resistance device formed of a resistive-change memory, wherein:
• the source of the first control transistor is electrically connected to the source of the second control transistor,
• the drain of the first control transistor is electrically connected to the drain of the second control transistor, and
• the gate of the first control transistor is electrically connected to the gate of the second control transistor.

The semiconductor memory device comprising:

• a global bit line;
• a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively;
• and
• a plurality of resistive-change memory cell groups storing data when connected to the local bit lines, respectively, wherein a resistive-change memory cell of each of the resistive-change memory cell groups comprises:
• a plurality of control transistors;
• and
• a variable resistance device formed of a resistive-change material, the variable resistance device coupled to each of the control transistors, wherein the plurality of control transistors are connected to each other in parallel wherein the resistive-change material is a phase change material;
• wherein the plurality of control transistors comprises:
• a first control transistor having first and second channel terminals, wherein the first channel terminal of the first control transistor is coupled to a first terminal of the variable resistance device, and wherein the second terminal of the first control transistor is connected to a reference potential;
• and
• a second control transistor having first and second channel terminals, wherein the first channel terminal of the second control transistor is coupled to the first terminal of the variable resistance device, and wherein the second terminal of the second control transistor is connected to the reference potential.