US 8,176,461 B1Granted

Design-specific performance specification based on a yield for programmable integrated circuits

AssigneeXilinx, Inc.

InventorStephen M. Trimberger

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Abstract

A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and second regions of the target device. A circuit design is placed and routed. With a programmed processor, the timing delay of the first timing specification is increased for one or more elements implementing the circuit design in the first region to produce a second timing specification, and a second timing yield of target device is determined from the second timing specification. In response to the second timing yield being larger than a target timing yield, the programmed processor decreases the timing delay of the second timing specification for one or more elements in the second region to compensate for a difference between the second timing yield and the target timing yield to produce a design-specific timing specification.

Claims15

Dependent claims

A method for determining a design-specific timing specification for elements of a target device, comprising:

inputting a placed-and-routed circuit design for a target device;
inputting a timing specification of delays for elements in different regions of the target device;
inputting an expected timing yield corresponding to the timing specification for a plurality of the target device;
wherein the expected timing yield is a first proportion of a total number of the plurality of the target device having all elements that satisfy the timing specification;
determining with a programmed processor a design-specific timing yield for the placed-and-routed circuit design as a function of amounts by which the delays of the timing specification are less than required delays of paths of the design;
wherein the design-specific timing yield is an expected second proportion of a total number of the plurality of the target device that, when configured with the circuit design, have all elements satisfying the timing specification;
selecting a path of the circuit design that uses elements in a first one of the regions;
and
reducing respective delays of a first set of one or more elements in the timing specification by respective amounts that maintain the design-specific timing yield at a level greater than or equal to the expected timing yield to produce a design-specific timing specification, the one or more timing elements being on the selected path in the first region.

6 more elements

A processor computing arrangement for determining a design-specific timing specification for elements of a target device, comprising:

a memory arrangement;
and
a processor coupled to the memory arrangement, the memory arrangement configured with program code that when executed by the processor causes the processor to perform operations comprising:
inputting a placed-and-routed circuit design for the target device;
inputting a timing specification of delays for elements in different regions of the target device;
inputting an expected timing yield corresponding to the timing specification for a plurality of the target device;
wherein the expected timing yield is a first proportion of a total number of the plurality of the target device having all elements that satisfy the timing specification;
determining with a programmed processor a design-specific timing yield for the placed-and-routed circuit design as a function of amounts by which the delays of the timing specification are less than required delays of paths of the design;
wherein the design-specific timing yield is an expected second proportion of a total number of the plurality of the target device that, when configured with the circuit design, have all elements satisfying the timing specification;
selecting a path of the circuit design that uses elements in a first one of the regions;
and
reducing respective delays of a first set of one or more elements in the timing specification by respective amounts that maintain the design-specific timing yield at a level greater than or equal to the expected timing yield to produce a design-specific timing specification, the one or more timing elements being on the selected path in the first region.

9 more elements

An article of manufacture, comprising:

a non-transitory processor-readable storage device storing processor-executable code for determining a design-specific timing specification for elements of a target device, the processor-executable code comprising instructions that when executed by a processor cause the processor to perform operations comprising:
inputting a placed-and-routed circuit design for the target device;
inputting a timing specification of delays for elements in different regions of the target device;
inputting an expected timing yield corresponding to the timing specification for a plurality of the target device;
wherein the expected timing yield is a first proportion of a total number of the plurality of the target device having all elements that satisfy the timing specification;
determining with a programmed processor a design-specific timing yield for the placed-and-routed circuit design as a function of amounts by which the delays of the timing specification are less than required delays of paths of the design;
wherein the design-specific timing yield is an expected second proportion of a total number of the plurality of the target device that, when configured with the circuit design, have all elements satisfying the timing specification;
selecting a path of the circuit design that uses elements in a first one of the regions;
and
reducing respective delays of a first set of one or more elements in the timing specification by respective amounts that maintain the design-specific timing yield at a level greater than or equal to the expected timing yield to produce a design-specific timing specification, the one or more timing elements being on the selected path in the first region.

7 more elements

Dependencies are inferred from the claim text.