Decoding/encoding method for booting from a NAND flash and system thereof
AssigneeMediatek Inc.
InventorsChin-Huo Chu, Horng-Yi Chang, Jia-Horng Shieh
Life of this patent
Estimating the term…
Abstract
A decoding method for booting from a NAND Flash including a booting page storing a plurality of copies of NAND booting information and a plurality of corresponding parities, each parity generated by an predetermined error correction code (ECC) bit number. The decoding method includes reading the booting page, for obtaining a plurality of configuration data and a plurality of ECC data, and performing a voting scheme and an ECC decoding process on the plurality of configuration data and the plurality of ECC data, for obtaining the NAND booting information. Besides, an encoding method for encoding such booting information is disclosed the same.
Claims20
A decoding method for booting from a NAND Flash comprising a booting page storing a plurality of copies of NAND booting information and a plurality of corresponding parities, each parity generated by a predetermined error correction code (ECC) bit number, the decoding method comprising:
- reading the booting page, for obtaining a plurality of configuration data and a plurality of ECC data;
- and
- performing a voting scheme and an ECC decoding process on the plurality of configuration data and the plurality of ECC data, for obtaining the NAND booting information.
An encoding method for a NAND Flash comprising:
- encoding NAND booting information according to a predetermined error correction code (ECC) capability, for generating a parity of a predetermined ECC bit number;
- duplicating the NAND booting information and the parity, for generating a plurality of NAND booting information and a plurality of parities;
- and
- writing the plurality of NAND booting information and the plurality of parities into a booting page of the NAND Flash.
A boot control system for booting from a NAND Flash including a booting page storing a plurality of copies of NAND booting information and a plurality of parities, each parity corresponding to the NAND booting information and corresponding to a predetermined error correction code (ECC) bit number, the boot control system comprising:
- a NAND flash controller, coupled to the NAND flash, for reading the booting page to obtain a plurality of configuration data and a plurality of ECC data;
- and
- a processing unit, coupled to the NAND flash controller, for performing a voting scheme and controlling an ECC engine to perform an ECC decoding process on the plurality of configuration data and the plurality of ECC data to obtain the NAND booting information.
Dependencies are inferred from the claim text.