Semiconductor memory having electrically floating body transistor

A semiconductor memory array comprising:

• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• and
• a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell, wherein said state of the memory cell is maintained relatively independent of a voltage applied to said gate.

A semiconductor memory cell comprising:

• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• and
• a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;
• wherein said cell is a multi-level cell, and wherein said floating body is configured to indicate more than one state by storing multi-bits.

A semiconductor memory array comprising:

• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• and
• a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;
• wherein each said cell is a multi-level cell, wherein each said floating body is configured to indicate more than one state by storing multi-bits.