Fully-differential amplifier circuit

A fully-differential amplifier circuit comprising:

• a differential amplifier configured to differentially amplify a first input signal and a second input signal serving as an input differential pair to generate a pair of a first intermediate signal and a second intermediate signal;
• a first class AB amplifier configured to amplify the first intermediate signal to generate a first output signal;
• and
• a second class AB amplifier configured to amplify the second intermediate signal to generate a second output signal,
• wherein the first output signal and the second output signal serve as an output differential pair,
• the first class AB amplifier amplifies the first intermediate signal with reference to a reference voltage adjusted by a first feedback signal that is a common mode component of the first output signal and the second output signal, and
• the second class AB amplifier amplifies the second intermediate signal with reference to a reference voltage adjusted by a second feedback signal that is a common mode component of the first output signal and the second output signal,
• wherein the first class AB amplifier includes:
• a first PMOS transistor which has a source connected to a power supply potential and is configured to output the first output signal from a drain thereof;
• a first NMOS transistor which has a source connected to a ground potential and a drain connected to a drain of the first PMOS transistor;
• a first transfer portion configured to transfer a first signal as a difference of the first intermediate signal with respect to a first reference signal to a gate of the first PMOS transistor;
• a second transfer portion configured to transfer a second signal as a difference of the first intermediate signal with respect to a second reference signal to a gate of the first NMOS transistor;
• and
• a first adjuster configured to receive the first output signal and the second output signal and adjust one of the first reference signal and the second reference signal using the first feedback signal, and
• the second class AB amplifier includes:
• a second PMOS transistor which has a source connected to the power supply potential and is configured to output the second output signal from a drain thereof;
• a second NMOS transistor which has a source connected to the ground potential and a drain connected to a drain of the second PMOS transistor;
• a third transfer portion configured to transfer a third signal as a difference of the second intermediate signal with respect to a third reference signal to a gate of the second PMOS transistor;
• a fourth transfer portion configured to transfer a fourth signal as a difference of the second intermediate signal with respect to a fourth reference signal to a gate of the second NMOS transistor;
• and
• a second adjuster configured to receive the first output signal and the second output signal and adjust one of the third reference signal and the fourth reference signal using the second feedback signal.