Calibration technique for measuring gate resistance of power MOS gate device at wafer level
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsAnup Bhalla, Sik K. Lui, Daniel Ng
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Abstract
This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
Claims8
A method for calibrating a MOSFET gate resistance measurement comprising:
- forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of MOSFET chips disposed on said semiconductor wafer;
- and
- said step of forming said RC network further comprises forming a resistance and capacitance of said RC network having a range approximately the same as a range of a MOSFET gate resistance Rg and a capacitance of said MOSFET chips.
A method for carrying out a wafer-level MOSFET measurement calibration comprising:
- forming a wafer-level measurement calibration circuit on a semiconductor wafer adjacent to a plurality MOSFET chips for carrying out said wafer-level MOSFET measurement calibration without connecting a drain of said MOSFET chips to a voltage source;
- and
- said step of forming said wafer-level measurement calibration circuit further comprising a step of forming RC network with a resistance and capacitance of said RC network having a range approximately the same as a range of a MOSFET gate resistance Rg and a capacitance of said MOSFET chips.
A method for calibrating a gate resistance measurement of a semiconductor power device comprising:
- forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of said RC network for carrying out a wafer-level measurement calibration of said semiconductor power device;
- and
- said step of forming said RC network further comprises forming a resistance and capacitance of said RC network having a range approximately the same as a range of a gate resistance Rg of said semiconductor power chips and a capacitance of said semiconductor power chips.
A method for carrying out a wafer-level semiconductor power device measurement calibration comprising:
- forming a wafer-level measurement calibration circuit on a semiconductor wafer adjacent to a plurality semiconductor power chips for carrying out said wafer-level measurement calibration without connecting a drain of said semiconductor power chips to a fixed voltage source;
- and
- said step of forming said RC network further comprises forming a resistance and capacitance of said RC network having a range approximately the same as a range of a gate resistance Rg of said semiconductor power chips and a capacitance of said semiconductor power chips.
Dependencies are inferred from the claim text.