# US 8,169,266 B2 · Mixer circuits and methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,169,266 B2 - Document ID: US8169266B2 - Status: Granted - Kind: B2 - Application number: 11/891,137 - Filed: 2007-08-08 - Published: 2007-12-06 - Granted: 2012-05-01 - Earliest claimed: 2005-04-14 - Assignees: WiLinx, Inc. - Inventors: Edris Rostami; Rahim Bagheri; Masoud Djafari; Abbas Komijani - Web page: https://patentgrep.com/patent/US8169266B2 ## CPC - H03D 7/1458: {Double balanced arrangements, i.e. where both input signals are differential} - H03D 7/1433: {using bipolar transistors (H03D7/145 takes precedence)} - H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)} - H03D 7/1483: {comprising components for selecting a particular frequency component of the output} - H03D 7/165: {at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002)} - H03D 2200/0043: Bias and operating point - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) ## Abstract Embodiments of the present invention include circuits and methods for improving the spectral purity of mixer circuits. In one embodiment the present invention includes a mixer circuit comprising a first transistor having a gate, a source and a drain, a second transistor having a gate, a source and a drain, a first capacitance coupled between the source of the first transistor and the source of the second transistor and a bias circuit having an input, a first output coupled to the source of the first transistor and a second output coupled to the source of the second transistor. The present invention may be advantageously used in a wireless transmitter application. ## Claims ### Claim 1 A mixer circuit comprising: a first transistor having a gate, a source, and a drain; a second transistor having a gate, a source, and a drain; a first capacitance coupled between the source of the first transistor and the source of the second transistor; and a bias circuit having an input, a first output coupled to the source of the first transistor, and a second output coupled to the source of the second transistor, wherein the bias circuit receives an input signal and generates first and second current signals on the first and second outputs, and wherein the first and second transistors are the mixer circuit core transistors which receive and mix a local oscillator (LO) signal and a mixer analog input signal coupled through the bias circuit. ### Claim 2 (depends on 1) The mixer circuit of claim 1 further comprising a load coupled to the drain of the first transistor and the drain of the second transistor. ### Claim 3 (depends on 1) The mixer circuit of claim 1 wherein the bias circuit includes a third transistor having a gate, a source and a drain and a fourth transistor having a gate, a source, and a drain, wherein the drain of the third transistor is coupled to the source of the first transistor and the drain of the fourth transistor is coupled to the source of the second transistor. ### Claim 4 (depends on 3) The mixer circuit of claim 3 wherein the bias circuit further includes at least one bias current source coupled to the source of the third transistor and the source of the fourth transistor. ### Claim 5 (depends on 1) The mixer circuit of claim 1 wherein the bias circuit includes a first resistor coupled to the source of the first transistor and a second resistor coupled to the source of the second transistor. ### Claim 6 (depends on 5) The mixer circuit of claim 5 wherein the first resistor is coupled between the source of the first transistor and a reference voltage and the second resistor is coupled between the source of the second transistor and the reference voltage. ### Claim 7 (depends on 5) The mixer circuit of claim 5 further comprising a second capacitance coupled to the source of the first transistor and a third capacitance coupled to the source of the second transistor. ### Claim 8 (depends on 7) The mixer circuit of claim 7 further comprising a voltage-to-current converter having an input that receives a voltage input signal and an output coupled to the second and third capacitance. ### Claim 9 (depends on 1) The mixer circuit of claim 1 wherein the gates of the first and second transistors are coupled to a local oscillator, the bias circuit input is coupled to a digital-to-analog converter and the drains of the first and second transistors are coupled to a driver circuit for transmitting an RF signal. ### Claim 10 (depends on 1) The mixer circuit of claim 1, the bias circuit comprising: a third transistor having a gate, a source, and a drain, wherein the drain of the third transistor is coupled to the source of the first transistor; a first sensing circuit coupled to the source of the third transistor; and a first comparison circuit coupled to the first sensing circuit, wherein the first comparison circuit receives a feedback signal from the first sensing circuit and a reference voltage, and in accordance therewith, generates a bias control signal to control the bias at the gate of the third transistor. ### Claim 11 (depends on 1) The mixer circuit of claim 1, the bias circuit comprising: a third transistor having a gate, a source, and a drain, wherein the drain of the third transistor is coupled to the source of the first transistor; a fourth transistor having a gate, a source, and a drain, wherein the drain of the fourth transistor is coupled to the source of the second transistor; a first circuit to control the current in the third transistor; a second circuit to control the current in the fourth transistor to match the current in the third transistor. ### Claim 12 A method comprising: receiving a first component of a differential signal at a gate of a first transistor, the first transistor further having a source, and a drain; receiving a second component of a differential signal at a gate of a second transistor, the second transistor further having a source, and a drain, wherein a first capacitance is coupled between the source of the first transistor and the source of the second transistor; and receiving a second signal in a bias circuit, the bias circuit having an input, a first output coupled to the source of the first transistor, and a second output coupled to the source of the second transistor, wherein the bias circuit receives the second signal and generates first and second current signals on the first and second outputs, and wherein the first and second transistors are mixer core transistors which receive and mix a local oscillator (LO) signal and a mixer analog input signal coupled through the bias circuit. ### Claim 13 (depends on 12) The method of claim 12 wherein a load is coupled to the drain of the first transistor and the drain of the second transistor. ### Claim 14 (depends on 12) The method of claim 12 wherein the bias circuit includes a third transistor having a gate, a source, and a drain, and a fourth transistor having a gate, a source, and a drain, wherein the drain of the third transistor is coupled to the source of the first transistor, and the drain of the fourth transistor is coupled to the source of the second transistor, the method further comprising: coupling the second signal to the gate of the third transistor; and coupling the second signal to the gate of the fourth transistor. ### Claim 15 (depends on 14) The method of claim 14 further comprising providing at least one bias current source to the source of the third transistor and the source of the fourth transistor. ### Claim 16 (depends on 12) The method of claim 12 wherein the bias circuit includes a first resistor coupled to the source of the first transistor, and a second resistor coupled to the source of the second transistor. ### Claim 17 (depends on 16) The method of claim 16 wherein the first resistor is coupled between the source of the first transistor and a reference voltage, and the second resistor is coupled between the source of the second transistor and the reference voltage. ### Claim 18 (depends on 16) The method of claim 16 wherein a second capacitance is coupled to the source of the first transistor, and a third capacitance is coupled to the source of the second transistor, the method further comprising: coupling the second signal through the second capacitance to the source of the first transistor; and coupling the second signal through the third capacitance to the source of the second transistor. ### Claim 19 (depends on 18) The method of claim 18 further comprising: receiving a voltage signal at an input of a voltage-to-current converter; and providing a current as the second signal at the output of the voltage-to-current converter to the second and third capacitance. ### Claim 20 (depends on 12) The method of claim 12 wherein the gates of the first and second transistors are coupled to a local oscillator, the bias circuit input is coupled to a digital-to-analog converter, and the drains of the first and second transistors are coupled to a driver circuit for transmitting an RF signal. ### Claim 21 A circuit comprising: a first transistor having a gate, a source, and a drain; a second transistor having a gate, a source, and a drain; a first capacitance coupled between the source of the first transistor and the source of the second transistor; a first bias circuit having an input, a first output coupled to the source of the first transistor, and a second output coupled to the source of the second transistor, wherein the first bias circuit receives a first input signal and generates first and second current signals on the first and second outputs of the first bias circuit to the source of the first transistor and the source of the second transistor; a third transistor having a gate, a source, and a drain; a fourth transistor having a gate, a source, and a drain; a second capacitance coupled between the source of the first transistor and the source of the second transistor; a second bias circuit having an input, a first output coupled to the source of the third transistor, and a second output coupled to the source of the fourth transistor, wherein the second bias circuit receives a second input signal and generates third and fourth current signals on the first and second outputs of the second bias circuit to the source of the third transistor and the source of the fourth transistor; a first load having a terminal coupled to the source of the first transistor and the source of the third transistor; and a second load having a terminal coupled to the source of the second transistor and the source of the fourth transistor.