Spintronic devices with integrated transistors
AssigneeMicron Technology, Inc.
InventorsRomney R. Katti, Theodore Zhu
Life of this patent
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Abstract
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.
Claims6
An SRAM integrated circuit comprising:
- at least two transistors, each of the transistors having a source terminal, a drain terminal, and a gate terminal;
- at least two magneto-resistive components (MRCs), each of the MRCs having an upper terminal and a lower terminal, wherein the MRCs can be selectively programmed to a state of high resistance or to a state of low resistance;
- and
- wherein the MRCs are coupled in series with the transistors, wherein the upper terminal of a first MRC is connected to a voltage source, wherein the lower terminal of the first MRC is connected to the source terminal of a first transistor, wherein the drain terminal of the first transistor is connected to the drain terminal of a second transistor, wherein the upper terminal of a second MRC is connected to the source terminal of the second transistor, and wherein the lower terminal of the second MRC is connected to a common ground terminal.
An SRAM integrated circuit comprising:
- at least two transistors, each of the transistors having a source terminal and a drain terminal;
- at least two magneto-resistive components (MRCs), each of the MRCs having an upper terminal and a lower terminal, wherein the MRCs can be selectively programmed to a state of high resistance or to a state of low resistance;
- and
- wherein the MRCs are coupled in series with the transistors, wherein the upper terminal of a first MRC is connected to a voltage source, wherein the lower terminal of the first MRC is connected to the source terminal of a first transistor, wherein the drain terminal of the first transistor is connected to the drain terminal of a second transistor, wherein the upper terminal of the second MRC is connected to the drain terminal of the first transistor, wherein the lower terminal of the second MRC is connected to the drain terminal of the second transistor, wherein the source terminal of the second transistor is connected to the ground terminal.
Dependencies are inferred from the claim text.