# US 8,151,238 B2 · Semiconductor integrated circuit and design method thereof

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- Number: US 8,151,238 B2
- Document ID: US8151238B2
- Status: Granted
- Kind: B2
- Application number: 12/943,549
- Filed: 2010-11-10
- Published: 2011-03-10
- Granted: 2012-04-03
- Earliest claimed: 2005-11-25
- Assignees: Panasonic Corporation
- Inventors: Kouji Fujiyama; Takahiro Nagatani; Atsushi Takahashi
- Web page: https://patentgrep.com/patent/US8151238B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.

## Claims

### Claim 1

A semiconductor integrated circuit comprising:
a first power supply source IO terminal;
a first power supply source wire; and
a first ring power supply, wherein:
the first power supply source IO terminal is connected to the first power supply source wire,
the first power supply source wire is connected to the first ring power supply,
the first power supply source wire includes a first branched wire, and
the first branched wire is connected to the first ring power supply.

### Claim 2 (depends on 1)

The semiconductor integrated circuit of claim 1, wherein
each of the first power supply source wire and the first branched wire includes a plurality of wire layers.

### Claim 3 (depends on 2)

The semiconductor integrated circuit of claim 2, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 4 (depends on 1)

The semiconductor integrated circuit of claim 1, further comprising:
a second power supply source IO terminal; and
a second power supply source wire, wherein:
the second power supply source IO terminal is connected to the second power supply source wire, and
the second power supply source wire is connected to the first ring power supply and the first branched wire.

### Claim 5 (depends on 4)

The semiconductor integrated circuit of claim 4, wherein
the second power supply source wire includes a plurality of wire layers.

### Claim 6 (depends on 5)

The semiconductor integrated circuit of claim 5, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 7 (depends on 4)

The semiconductor integrated circuit of claim 4, wherein:
the first power supply source wire further includes a second branched wire, and
the second power supply source wire is connected to the second branched wire.

### Claim 8 (depends on 7)

The semiconductor integrated circuit of claim 7, wherein
each of the second power supply source wire and the second branched wire includes a plurality of wire layers.

### Claim 9 (depends on 8)

The semiconductor integrated circuit of claim 8, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 10 (depends on 4)

The semiconductor integrated circuit of claim 4, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 11 (depends on 7)

The semiconductor integrated circuit of claim 7, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 12 (depends on 4)

The semiconductor integrated circuit of claim 4, wherein
a total number of connection points of the first power supply source wire to the first ring power supply, connection points of the second power supply source wire to the first ring power supply, and connection points of the first branched wire to the first ring power supply is larger than a total number of the first power supply source IO terminal and the second power supply source IO terminal.

### Claim 13 (depends on 12)

The semiconductor integrated circuit of claim 12, wherein
the second power supply source wire includes a plurality of wire layers.

### Claim 14 (depends on 13)

The semiconductor integrated circuit of claim 13, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 15 (depends on 12)

The semiconductor integrated circuit of claim 12, wherein:
the first power supply source wire further includes a second branched wire, and
the second power supply source wire is connected to the second branched wire.

### Claim 16 (depends on 15)

The semiconductor integrated circuit of claim 15, wherein
each of the second power supply source wire and the second branched wire includes a plurality of wire layers.

### Claim 17 (depends on 16)

The semiconductor integrated circuit of claim 16, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 18 (depends on 15)

The semiconductor integrated circuit of claim 15, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 19 (depends on 12)

The semiconductor integrated circuit of claim 12, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.

### Claim 20 (depends on 1)

The semiconductor integrated circuit of claim 1, further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.