# US 8,151,153 B1 · Scan architecture for full custom blocks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,151,153 B1 - Document ID: US8151153B1 - Status: Granted - Kind: B1 - Application number: 13/093,114 - Filed: 2011-04-25 - Granted: 2012-04-03 - Earliest claimed: 2006-09-19 - Assignees: Marvell International Ltd. - Inventors: Manish Shrivastava - Web page: https://patentgrep.com/patent/US8151153B1 ## CPC - G01R 31/318541: {Scan latches or cell details} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability. ## Claims ### Claim 1 A combinational logic circuit, comprising: an input latch that controls passage of a binary input data signal through the input latch based on a master phase clock signal of a two-phase clock; a combinational logic that receives the binary input data signal passed by the input latch and generates an output data signal based on applying the combinational logic to the received binary input data signal; a passthrough switch that controls passage of the output data signal through the passthrough switch based on a slave phase clock signal of the two-phase clock; and an output storage circuit that receives the output data signal from the passthrough switch and stores a binary output data signal value based a level of the received output data by controlling a connection between the output storage circuit and a low logic signal source based on the slave phase clock signal of the two-phase clock. ### Claim 2 (depends on 1) The combinational logic circuit of claim 1 further corn irises a semi-fighting latch including the output storage circuit, wherein the semi-fighting latch is non-fighting for a change from low to high at an input node of the semi-fighting latch, and the semi-fighting latch is fighting for a change from high to low at the input node of the semi-fighting latch. ### Claim 3 (depends on 2) The combinational logic circuit of claim 2, wherein the semi-fighting latch, in a first operation mode, performs to support a functional processing performed by the combinational logic circuit, and in a second mode, performs to support a scan chain testing performed by the combinational logic circuit. ### Claim 4 (depends on 3) The combinational logic circuit of claim 3, wherein the second mode includes a scan chain test preparation mode in which a sequence of test input data is received and passed along a scan chain in preparation for a test. ### Claim 5 (depends on 4) The combinational logic circuit of claim 4, wherein the second mode further includes a scan chain test execution mode in which the sequence of test input data is passed to the combinational logic circuit for execution, and outputs generated by the combinational logic circuit is stored in the semi-fighting latch. ### Claim 6 (depends on 5) The combinational logic circuit of claim 5, wherein the second mode further includes a scan chain test output mode in which received scan chain test results are sequentially passed and outputted to a test result register. ### Claim 7 An integrated circuit, comprising: a plurality of input latches, wherein each input latch controls passage of a binary input data value to a combinational logic, the input latches opening and closing based on a value of a master phase clock signal of a two-phase clock; and a plurality of output latches, wherein each output latch controls passage of a binary output data value from the combinational logic, the output latches opening and closing based on a value of a slave phase clock signal of the two-phase clock, each output latch further comprising: an output storage circuit that controls a connection between the output storage circuit and a low logic signal source based on the value of the slave phase clock signal of the two-phase clock. ### Claim 8 (depends on 7) The integrated circuit of claim 7 further comprises a semi-fighting latch including the output storage circuit, wherein the semi-fighting latch is non-fighting for a change from low to high at an input node of the semi-fighting latch, and the semi-fighting latch is fighting for a change from high to low at the input node of the semi-fighting latch. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the semi-fighting latch, in a first operation mode, performs to support a functional processing performed by the combinational logic, and in a second mode, performs to support a scan chain testing performed by the combinational logic. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the second mode includes a scan chain test preparation mode in which a sequence of test input data is received and passed along a scan chain in preparation for a test. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the second mode further includes a scan chain test execution mode in which the sequence of test input data is passed to the combinational logic for execution, and outputs generated by the combinational logic is stored in the semi-fighting latch. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the second mode further includes a scan chain test output mode in which received scan chain test results are sequentially passed and outputted to a test result register.