Data transfer between chips in a multi-chip semiconductor device with an increased data transfer speed

A multi-chip semiconductor device comprising:

• two or more semiconductor chips;
• a plurality of inter-chip wires through which data are transferred between the chips in synchronization with a clock signal;
• inter-chip wire testing means for conducting a test to determine whether or not each inter-chip wire is capable of normally transferring data;
• at least one buffer circuit on a chip on a transmission side and which is connected to an inter-chip wire, for transferring data to be transferred through the inter-chip wire to a chip on a reception side at a first data transfer speed in synchronization with said clock signal to the chip on the reception side, or for transferring said data to be transferred to the chip on the reception side through the inter-chip wire and data to be transferred to the chip on the reception side through another inter-chip wire at a second data transfer speed obtained by multiplying the first data transfer speed by the number of these data, to the chip on the reception side;
• and
• transfer speed control means for, when there exists an inter-chip wire incapable of normally transferring data, as a result of said test, switching the data transfer speed of said buffer circuit from the first data transfer speed to the second data transfer speed, and causing said buffer circuit to transfer data which cannot be transferred through the inter-chip wire to the chip on the reception side through the inter-chip wire connected to said buffer circuit.