# US 8,149,637 B2 · Semiconductor device capable of being tested after packaging > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,149,637 B2 - Document ID: US8149637B2 - Status: Granted - Kind: B2 - Application number: 12/698,672 - Filed: 2010-02-02 - Published: 2010-11-25 - Granted: 2012-04-03 - Earliest claimed: 2009-05-20 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Hee-Il Hong; Kang-Young Cho - Web page: https://patentgrep.com/patent/US8149637B2 ## CPC - G11C 29/50: Marginal testing, e.g. race, voltage or current testing - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 29/50016: {of retention} - G11C 2029/1202: {Word line control} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines. ## Claims ### Claim 1 A semiconductor device comprising: a memory cell array including a plurality of memory cells; an external test pad connected to an internal test pad; an external pad connected to an internal pad; and a first connection unit connecting the internal pad and the internal test pad in a normal mode and disconnecting the internal pad and the internal test pad in a test mode, in response to a first control signal, wherein, a test voltage is applied to a plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in the test mode, the test voltage disables the plurality of word lines, and a ground voltage is applied to the semiconductor device via the external pad and the internal pad. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the test voltage is a negative voltage. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first connection unit is a switch. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising: a voltage generator generating a predetermined voltage, connected to the plurality of word lines; and a second connection unit connecting the voltage generator and the internal test pad in the test mode and disconnecting the voltage generator and the internal test pad in the normal mode, in response to a second control signal, wherein, the test voltage is applied to the plurality of word lines via the external test pad and the internal test pad in the test mode, if the voltage generator is disabled, the predetermined voltage or the test voltage is applied to the plurality of word lines in the test mode, if the voltage generator is enabled, and the predetermined voltage is applied to the plurality of word lines via the voltage generator in the normal mode. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the predetermined voltage is a negative voltage. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein the second connection unit is a switch. ### Claim 7 (depends on 4) The semiconductor device of claim 4, wherein the second control signal is a mode register set (MRS) signal. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the ground voltage is applied to the plurality of word lines via the external test pad and the internal test pad in the normal mode. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the first control signal is a mode register set (MRS) signal. ### Claim 10 A memory system apparatus comprising: a memory device including a semiconductor device and a controller controlling the memory device, wherein the semiconductor device comprises: a memory cell array including a plurality of memory cells; an external test pad connected to an internal test pad; an external pad connected to an internal pad; and a first connection unit connecting the internal pad and the internal test pad in a normal mode and disconnecting the internal pad and the internal test pad in a test mode, in response to a first control signal, wherein, a test voltage is applied to a plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in the test mode, the test voltage disables the plurality of word lines, and a ground voltage is applied to the semiconductor device via the external pad and the internal pad. ### Claim 11 (depends on 10) The memory system apparatus of claim 10, wherein the test voltage is a negative voltage. ### Claim 12 (depends on 10) The memory system apparatus of claim 10, wherein the semiconductor device further comprises: a voltage generator generating a predetermined voltage, connected to the plurality of word lines; and a second connection unit connecting the voltage generator and the internal test pad in the test mode and disconnecting the voltage generator and the internal test pad in the normal mode, in response to a second control signal, wherein, the test voltage is applied to the plurality of word lines via the external test pad and the internal test pad in the test mode, if the voltage generator is disabled, the predetermined voltage or the test voltage is applied to the plurality of word lines in the test mode, if the voltage generator is enabled, and the predetermined voltage is applied to the plurality of word lines via the voltage generator in the normal mode. ### Claim 13 (depends on 10) The memory system apparatus of claim 10, wherein the ground voltage is applied to the plurality of word lines via the external test pad and the internal test pad in the normal mode. ### Claim 14 A method for testing a semiconductor device, comprising the steps of: applying a ground voltage to the semiconductor device via an external pad and an internal pad; applying a test voltage to a plurality of word lines connected to a plurality of memory cells of a memory cell array, via an external test pad and an internal test pad, in a test mode, wherein the test voltage disables the plurality of word lines; applying the ground voltage to the plurality of word lines in a normal mode, wherein, a control signal received by a connection unit determines whether the semiconductor device is in the test mode or the normal mode; applying the test voltage to the plurality of word lines via the external test pad and the internal test pad in the test mode, if a voltage generator is disabled; applying a predetermined voltage to the plurality of word lines via the voltage generator in the test mode, if the voltage generator is enabled; and applying the predetermined voltage to the plurality of word lines via the voltage generator in the normal mode.