# US 8,149,634 B2 · Low power memory architecture

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- Number: US 8,149,634 B2
- Document ID: US8149634B2
- Status: Granted
- Kind: B2
- Application number: 12/470,877
- Filed: 2009-05-22
- Published: 2009-09-17
- Granted: 2012-04-03
- Earliest claimed: 2006-02-28
- Assignees: Mosaid Technologies Incorporated
- Inventors: Valerie L. Lines
- Web page: https://patentgrep.com/patent/US8149634B2

## CPC

- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 2207/065: Sense amplifier drivers
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.

## Claims

### Claim 1

A datapath circuit comprising:
a databus;
a precharge circuit for selectively precharging the databus to a first voltage during an idle period and a second voltage in an active period; and,
a plurality of data transfer circuits each selectable for connecting the databus to the first voltage in response to data in the active period.

### Claim 2 (depends on 1)

The datapath circuit of claim 1, wherein the precharge circuit includes
a pull-up circuit for precharging the databus to the second voltage in the active period, and,
a pull-down circuit for precharging the databus to the first voltage during the idle period.

### Claim 3 (depends on 1)

The datapath circuit of claim 1, wherein the databus includes true and complementary datalines.

### Claim 4 (depends on 3)

The datapath circuit of claim 3, wherein the pull-up circuit includes a first pull-up transistor pair for connecting the true dataline and the complementary dataline to the second voltage.

### Claim 5 (depends on 4)

The datapath circuit of claim 4, wherein the pull-down circuit includes a pull-down transistor pair for connecting the true dataline and the complementary dataline to the first voltage.

### Claim 6

A method for low power datapath operation comprising:
a) precharging a databus pair from a first voltage to a second voltage in an active period;
b) driving one of the databus pair to the first voltage in response to data during the active period; and,
c) precharging the databus pair to the first voltage in an idle period after the active period has ended.

### Claim 7 (depends on 6)

The method of claim 6, wherein the step of precharging the databus pair to the second voltage includes disabling pull-down down transistors coupled between the databus pair and the first voltage, before enabling pull-up transistors coupled between the databus pair and the second voltage.

### Claim 8 (depends on 7)

The method of claim 7, wherein the step of precharging the databus pair to the first voltage includes disabling the pull-up transistors before enabling the pull-down transistors.