# US 8,149,632 B2 · Output circuit for a semiconductor memory device and data output method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,149,632 B2 - Document ID: US8149632B2 - Status: Granted - Kind: B2 - Application number: 12/707,140 - Filed: 2010-02-17 - Published: 2010-06-10 - Granted: 2012-04-03 - Earliest claimed: 2007-05-25 - Assignees: Elpida Memory, Inc. - Inventors: Yoshinori Matsui - Web page: https://patentgrep.com/patent/US8149632B2 ## CPC - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell. ## Claims ### Claim 1 A semiconductor device comprising: a terminal; first and second voltage lines supplied respectively with first and second potentials, the first potential being larger than the second potential; an output circuit comprising a first transistor of a first conductivity type coupled between the first voltage line and the terminal and a second transistor of a second conductivity type coupled between the second voltage line and the terminal; a gate level setting section coupled to the first and second transistors to control levels of control electrodes of the first and second transistors; and a core circuit producing information which is to be outputted at the terminal through the gate level setting section and the output circuit, the core circuit comprising a third transistor of the first conductivity type; the first transistor having a threshold value that is smaller in absolute value than a threshold value of the third transistor; the gate level setting section supplying the control electrode of the first transistor with a third potential that is larger than the first potential in a stand-by mode in which both of the first and second transistors are rendered non-conductive to prevent the information from the core circuit from being outputted at the terminal and with the first potential in an active mode in which one of the first and second transistors is rendered conductive to allow the information from the core circuit to be outputted at the terminal. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the gate level setting section supplies, in the stand-by mode, the control electrode of the second transistor with a potential that is smaller than the first potential. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the gate level setting section supplies, in the active mode, the control electrode of the second transistor with a potential that is larger than or equal to the first potential. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the gate level setting section comprises: a first buffer configured with a transistor of the first conductivity type and a transistor of the second conductivity type and supplying the control electrode of the first transistor with a first signal corresponding to the information; and a second buffer configured with a transistor of the first conductivity type and a transistor of the second conductivity type and supplying the control electrode of the second transistor with a second signal corresponding to the information. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the gate level setting section further comprises a fourth transistor and a fifth transistor, the transistor of the first conductivity type that configures the first buffer and the fourth transistor that is controlled so as to be rendered electrically conductive in the active mode are coupled in series between the control electrode of the first transistor and the first voltage line, and the transistor of the first conductivity type that configures the first buffer and the fifth transistor that is controlled so as to be rendered electrically conductive in the stand-by mode are coupled in series between the control electrode of the first transistor and a third voltage line supplied with the third potential. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein a drain of the fourth transistor and a drain of the fifth transistor are coupled to a source of the transistor of the first conductivity type that configures the first buffer. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein the fifth transistor is a transistor of the first conductivity type. ### Claim 8 (depends on 5) The semiconductor device according to claim 5, wherein a threshold value of the transistor of the first conductivity type that configures the first buffer is equal to the threshold value of the first transistor. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the fourth transistor is a transistor of the second conductivity type, and in the active mode, a control electrode of the fourth transistor is supplied with a fourth potential that is larger than the third potential. ### Claim 10 (depends on 5) The semiconductor device according to claim 5, wherein the gate level setting section further comprises a first resistor coupled in series to the transistor of the first conductivity type that configures the first buffer and to the fifth transistor between the third voltage line and a source of the transistor of the first conductivity type that configures the first buffer. ### Claim 11 (depends on 4) The semiconductor device according to claim 4, wherein the gate level setting section further comprises a sixth transistor coupled to the control electrode of the first transistor and supplying, in the stand-by mode, the control electrode of the first transistor with the third potential. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the gate level setting section further comprises a second resistor coupled in series to the sixth transistor between a third voltage line supplied with the third potential and the control electrode of the first transistor. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein the gate level setting section further comprises a seventh transistor, and the transistor of the first conductivity type that configures the first buffer and the seventh transistor that is controlled so as to be rendered electrically non-conductive in the stand-by mode are coupled in series between the control electrode of the first transistor and the first voltage line. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the seventh transistor is a transistor of the second conductivity type, and in the active mode, a control electrode of the seventh transistor is supplied with a fourth potential that is larger than the third potential. ### Claim 15 (depends on 11) The semiconductor device according to claim 11, further comprising first and second external terminals to which the first and third potentials are respectively supplied from an outside of the semiconductor device independently, the first and second external terminals being respectively coupled to the first voltage line and a third voltage line supplied with the third potential, wherein the semiconductor device has a first state at a time power is turned on, the first state indicating a period in which the first potential is supplied from the outside at an earlier time than the third potential, and the gate level setting section further comprises: an eighth transistor and a ninth transistor respectively coupled to the control electrode of the first transistor and the control electrode of the second transistor, the eighth transistor and the ninth transistor controlling, in the first state, both the first transistor and the second transistor to render both the first transistor and the second transistor electrically non-conductive; and a control circuit controlling the eighth transistor and the ninth transistor. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the control circuit comprises: first and second input terminals respectively coupled to the first and second external terminals; and an output terminal supplying the eighth transistor and the ninth transistor with a third signal, and the third signal has first and second logics related to a correlation between the respective potentials of the first and second external terminals. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the eighth transistor is a transistor of the second conductivity type coupled between the first voltage line and the control electrode of the first transistor, and the ninth transistor is a transistor of the second conductivity type coupled between the second voltage line and the control electrode of the second transistor. ### Claim 18 (depends on 16) The semiconductor device according to claim 16, wherein the control circuit comprises a tenth transistor of the first conductivity type and an eleventh transistor of the second conductivity type, the tenth transistor and the eleventh transistor being coupled in series between the first voltage line and the second voltage line, respective control electrodes of the tenth transistor and the eleventh transistor being coupled to the third voltage line, respective drains of the tenth transistor and the eleventh transistor being coupled to the output terminal. ### Claim 19 (depends on 15) The semiconductor device according to claim 15, wherein the gate level setting section further comprises a twelfth transistor, and the transistor of the first conductivity type that configures the second buffer and the twelfth transistor are coupled in series between the control electrode of the second transistor and the first voltage line, a control electrode of the twelfth transistor being supplied with a potential that is larger than or equal to the third potential. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the twelfth transistor is a transistor of the second conductivity type, and the control electrode of the twelfth transistor is supplied with a fourth potential that is larger than the third potential. ### Claim 21 (depends on 9) The semiconductor device according to claim 9, further comprising a potential generation circuit coupled to a third voltage line supplied with the third potential, the potential generation circuit generating the fourth potential from the third potential. ### Claim 22 (depends on 14) The semiconductor device according to claim 14, further comprising a potential generation circuit coupled to a third voltage line supplied with the third potential, the potential generation circuit generating the fourth potential from the third potential. ### Claim 23 (depends on 20) The semiconductor device according to claim 20, further comprising a potential generation circuit coupled to a third voltage line supplied with the third potential, the potential generation circuit generating the fourth potential from the third potential. ### Claim 24 (depends on 4) The semiconductor device according to claim 4, wherein a threshold value of the transistor of the first conductivity type that configures the first buffer and a threshold value of the transistor of the first conductivity type that configures the second buffer are smaller in absolute value than the threshold value of the third transistor of the first conductivity type included in the core circuit. ### Claim 25 (depends on 1) The semiconductor device according to claim 1, wherein the gate level setting section independently supplies the respective control electrodes of the first and second transistors with a plurality of potentials.